[RISCV] Legalize fixed-baseline RV64 MachineIR

5 files changed, 31 insertions, 7 deletions

diff --git a/backend/unittests/CodeGen/GenericOpcodesTest.cpp b/backend/unittests/CodeGen/GenericOpcodesTest.cpp
index 36cc6ca..2463fce 100644
--- a/backend/unittests/CodeGen/GenericOpcodesTest.cpp
+++ b/backend/unittests/CodeGen/GenericOpcodesTest.cpp
@@ -282,13 +282,14 @@ void testShapesAndTypes(TestContext &Context) {
   auto I32 = rcc::LLT::makeInteger(32);
   auto I64 = rcc::LLT::makeInteger(64);
   auto I1 = rcc::LLT::makeInteger(1);
+  auto S16 = rcc::LLT::makeAnyScalar(16);
   auto F32 = rcc::LLT::makeFloat(rcc::FloatSemantics::IEEESingle);
   auto F64 = rcc::LLT::makeFloat(rcc::FloatSemantics::IEEEDouble);
   auto P64 = rcc::LLT::makePointer(0, 64);
   auto V2I32 = I32 ? rcc::LLT::makeFixedVector(2, *I32) : rcc::Expected<rcc::LLT>{};
   auto V4I32 = I32 ? rcc::LLT::makeFixedVector(4, *I32) : rcc::Expected<rcc::LLT>{};
   auto V2P64 = P64 ? rcc::LLT::makeFixedVector(2, *P64) : rcc::Expected<rcc::LLT>{};
-  if (!I1 || !I32 || !I64 || !F32 || !F64 || !P64 || !V2I32 || !V4I32 || !V2P64)
+  if (!I1 || !I32 || !I64 || !S16 || !F32 || !F64 || !P64 || !V2I32 || !V4I32 || !V2P64)
     std::terminate();
   auto Dst32 = (*Function)->registerInfo().createVirtualRegister(*I32);
   auto Src32A = (*Function)->registerInfo().createVirtualRegister(*I32);
@@ -299,6 +300,7 @@ void testShapesAndTypes(TestContext &Context) {
   const rcc::Register Cond = createVirtualRegister(**Function, *I1);
   const rcc::Register Float32 = createVirtualRegister(**Function, *F32);
   const rcc::Register Float64 = createVirtualRegister(**Function, *F64);
+  const rcc::Register Scalar16 = createVirtualRegister(**Function, *S16);
   const rcc::Register Vec2A = createVirtualRegister(**Function, *V2I32);
   const rcc::Register Vec2B = createVirtualRegister(**Function, *V2I32);
   const rcc::Register Vec4 = createVirtualRegister(**Function, *V4I32);
@@ -319,6 +321,17 @@ void testShapesAndTypes(TestContext &Context) {
                                                 (*Function)->registerInfo()),
                  "G_ADD must reject a source from a different LLT equality group");
 
+  auto ZeroImmediate = rcc::IntegerImmediate::fromUnsigned(64, 0);
+  std::vector<rcc::MachineOperand> PointerConstant;
+  PointerConstant.push_back(registerOperand(*Address, true));
+  if (ZeroImmediate)
+    PointerConstant.push_back(rcc::MachineOperand::integerImmediate(std::move(*ZeroImmediate)));
+  Context.expect(PointerConstant.size() == 2 &&
+                     Set->validateExplicitOperands(rcc::opcode(rcc::GenericOpcode::G_CONSTANT),
+                                                   PointerConstant, (*Function)->registerInfo())
+                         .has_value(),
+                 "G_CONSTANT must accept a scalar pointer destination");
+
   auto Block0 = (*Function)->createBasicBlock();
   auto Block1 = (*Function)->createBasicBlock();
   if (!Block0 || !Block1 || !(*Function)->appendBlock(**Block0) ||
@@ -474,6 +487,17 @@ void testShapesAndTypes(TestContext &Context) {
   Context.expect(!Set->validateExplicitOperands(rcc::opcode(rcc::GenericOpcode::G_FCONSTANT),
                                                 FConstantOperands, (*Function)->registerInfo()),
                  "G_FCONSTANT must reject mismatched floating semantics");
+
+  const std::array<std::uint64_t, 1> BFloatWords{0};
+  auto BFloatBits = rcc::FloatingPointBits::create(rcc::FloatSemantics::BFloat, BFloatWords);
+  if (!BFloatBits)
+    std::terminate();
+  FConstantOperands[0] = registerOperand(Scalar16, true);
+  FConstantOperands[1] = rcc::MachineOperand::floatingImmediate(*BFloatBits);
+  Context.expect(Set->validateExplicitOperands(rcc::opcode(rcc::GenericOpcode::G_FCONSTANT),
+                                               FConstantOperands, (*Function)->registerInfo())
+                     .has_value(),
+                 "G_FCONSTANT must accept a bit-width-compatible LLVM scalar LLT");
 }
 
 void testInstructionMemorySemantics(TestContext &Context) {
diff --git a/backend/unittests/Target/Inputs/RISCVDataPipeline.mir b/backend/unittests/Target/Inputs/RISCVDataPipeline.mir
index f847640..0d0c35d 100644
--- a/backend/unittests/Target/Inputs/RISCVDataPipeline.mir
+++ b/backend/unittests/Target/Inputs/RISCVDataPipeline.mir
@@ -13,6 +13,6 @@ jumpTable:
 body: |
   bb.0:
     liveins: $x1
-    %0:gpr(i64) = G_CONSTANT 7
+    %0:gprb(i64) = G_CONSTANT 7
     $x10 = COPY %0
     PseudoRET implicit $x1, implicit $x10
diff --git a/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir
index d68cd72..62c1baf 100644
--- a/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir
+++ b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir
@@ -5,8 +5,8 @@ isSSA: true
 body: |
   bb.0:
     liveins: $x1
-    %0:gpr(i64) = G_CONSTANT 42
-    %1:gpr(i64) = G_CONSTANT 1
-    %2:gpr(i64) = G_ADD %0, %1
+    %0:gprb(i64) = G_CONSTANT 42
+    %1:gprb(i64) = G_CONSTANT 1
+    %2:gprb(i64) = G_ADD %0, %1
     $x10 = COPY %2
     PseudoRET implicit $x1, implicit $x10
diff --git a/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir b/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir
index 3105fe4..4f37d15 100644
--- a/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir
+++ b/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir
@@ -7,6 +7,6 @@ stack:
 body: |
   bb.0:
     liveins: $x1
-    %0:gpr(i64) = G_CONSTANT 9
+    %0:gprb(i64) = G_CONSTANT 9
     $x10 = COPY %0
     PseudoRET implicit $x1, implicit $x10
diff --git a/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir b/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir
index 9695691..1b9ee82 100644
--- a/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir
+++ b/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir
@@ -5,6 +5,6 @@ isSSA: true
 body: |
   bb.0:
     liveins: $x1
-    %0:gpr(i64) = G_CONSTANT 9223372036854775807
+    %0:gprb(i64) = G_CONSTANT 9223372036854775807
     $x10 = COPY %0
     PseudoRET implicit $x1, implicit $x10