backend/unittests/Target/Inputs/RISCVGenericPipeline.mir


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---
name: generic_pipeline
tracksRegLiveness: true
isSSA: true
body: |
  bb.0:
    liveins: $x1
    %0:gpr(i64) = G_CONSTANT 42
    %1:gpr(i64) = G_CONSTANT 1
    %2:gpr(i64) = G_ADD %0, %1
    $x10 = COPY %2
    PseudoRET implicit $x1, implicit $x10