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* [Tooling] Remove the duplicate output kindRichard-Qin-X2026-08-132-25/+22
* [RISCV] Use the generated opcode conversionRichard-Qin-X2026-08-132-25/+30
* [TableGen] Split the target description generatorRichard-Qin-X2026-08-132-10/+7
* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-134-85/+108
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-1311-34/+33
* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-135-6/+10
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1325-1035/+1009
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-1317-993/+1199
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-136-1187/+1221
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-1214-220/+211
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-127-703/+810
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-124-50/+169
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-121-1/+1
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-122-21/+7
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-123-11/+13
* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-121-0/+30
* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-121-0/+5
* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-121-2/+13
* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-3/+12
* [clang-format] Format MIR sourcesRichard-Qin-X2026-08-121-5/+4
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-125-38/+66
* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-123-6/+39
* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-121-0/+25
* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-1/+5
* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-121-2/+12
* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-121-0/+6
* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-0/+27
* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+50
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-122-13/+96
* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-0/+32
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-122-3/+87
* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-4/+5
* [MIR] Create virtual registers referenced by live-insRichard-Qin-X2026-08-121-0/+43
* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-121-3/+25
* [CodeGen] Test cloning unnamed functionsRichard-Qin-X2026-08-121-5/+5
* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-7/+15
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-122-6/+29
* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-121-0/+31
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-1/+1
* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-1/+12
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-1/+1
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-122-3/+51
* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-121-2/+3
* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-121-1/+2
* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-121-2/+3
* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+41
* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-0/+6
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-117-78/+120
* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-111-7/+20
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-114-13/+47
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 14:41:56 +0000