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* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-261-1/+2
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-224-7/+146
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-223-1/+225
* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-191-2/+1
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-193-1/+342
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-191-1/+2
* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-192-0/+20
* [RISCV][GlobalISel] Match floating comparisonsRichard-Qin-X2026-08-192-0/+60
* [RISCV][GlobalISel] Generate indirect branch selectionRichard-Qin-X2026-08-192-0/+17
* [RISCV][GlobalISel] Generate conditional branch selectionRichard-Qin-X2026-08-172-1/+17
* [RISCV][GlobalISel] Generate implicit-def selectionRichard-Qin-X2026-08-171-5/+10
* [RISCV][GlobalISel] Generate integer extension selectionsRichard-Qin-X2026-08-172-64/+89
* [RISCV][GlobalISel] Generate shift selectionsRichard-Qin-X2026-08-162-7/+137
* [RISCV][GlobalISel] Generate integer comparisonsRichard-Qin-X2026-08-162-58/+198
* [RISCV][GlobalISel] Select comparisons against zeroRichard-Qin-X2026-08-162-1/+210
* tablegen: Generate GlobalISel match tablesRichard-Qin-X2026-08-163-1/+227
* [RISCV][GlobalISel] Legalize floating-point to integer conversionsRichard-Qin-X2026-08-152-0/+14
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-1/+2
* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-132-0/+6
* [TableGen] Split the target description generatorRichard-Qin-X2026-08-135-0/+1331