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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-13108-2534/+2435
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-1364-2604/+3051
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-1313-1723/+1917
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-1250-6937/+7097
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-1224-1633/+2003
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-1223-347/+366
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-1221-54/+66
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-127-392/+0
* [Testing] Add the LLVM MIR RUN executorRichard-Qin-X2026-08-121-0/+682
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-1221-335/+620
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-1214-100/+202
* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-122-3/+103
* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-122-1/+6
* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-123-3/+100
* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-122-3/+89
* [clang-format] Format MIR sourcesRichard-Qin-X2026-08-123-18/+15
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-1222-122/+94
* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-126-8/+292
* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-122-1/+26
* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-122-3/+7
* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-123-55/+15
* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-122-6/+8
* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-122-2/+29
* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-122-0/+54
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-124-38/+288
* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-122-15/+47
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-125-3/+200
* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-122-5/+6
* [MIR] Create virtual registers referenced by live-insRichard-Qin-X2026-08-124-6/+57
* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-123-12/+33
* [CodeGen] Test cloning unnamed functionsRichard-Qin-X2026-08-121-5/+5
* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-122-7/+65
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-125-7/+129
* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-122-16/+64
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-122-1/+16
* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-122-5/+24
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-122-1/+164
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-128-15/+97
* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-122-6/+9
* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-122-4/+6
* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-123-9/+20
* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-112-0/+52
* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-112-2/+8
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-1114-155/+303
* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-112-15/+28
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-119-69/+146
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-1110-46/+18
* [RISCV] Derive the generated instruction count in testsRichard-Qin-X2026-08-111-1/+5
* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-116-85/+80
* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-112-7/+15
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