rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[CodeGen] Reuse register diagnostic formatting	Richard-Qin-X	2026-08-13	1	-2/+1
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*	[CodeGen] Avoid unchecked memory alignment access	Richard-Qin-X	2026-08-13	1	-2/+2
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*	[Tooling] Restrict tidy to backend sources	Richard-Qin-X	2026-08-13	1	-2/+1
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*	[CodeGen] Inline liveness test helpers	Richard-Qin-X	2026-08-13	1	-16/+16
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*	[CodeGen] Remove duplicate analysis declarations	Richard-Qin-X	2026-08-13	2	-5/+0
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*	[IR] Sequence analysis registration moves	Richard-Qin-X	2026-08-13	1	-2/+3
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*	[TableGen] Fix quality tool source paths	Richard-Qin-X	2026-08-13	2	-0/+2
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*	[Tooling] Remove the duplicate output kind	Richard-Qin-X	2026-08-13	10	-202/+108
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*	[RISCV] Remove physical register forwarding helpers	Richard-Qin-X	2026-08-13	3	-57/+39
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*	[RISCV] Use the generated opcode conversion	Richard-Qin-X	2026-08-13	11	-220/+198
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*	[Support] Centralize error context handling	Richard-Qin-X	2026-08-13	30	-234/+119
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*	[CodeGen] Remove the unused property query	Richard-Qin-X	2026-08-13	2	-5/+0
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*	[TableGen] Split the target description generator	Richard-Qin-X	2026-08-13	30	-3161/+3516
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*	[IR] Split LL parsing, assembly writing, and data layout	Richard-Qin-X	2026-08-13	28	-2414/+2404
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*	[Support] Split APInt and APFloat ownership	Richard-Qin-X	2026-08-13	34	-2004/+1994
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*	[CodeGen] Align MIR parser and printer ownership	Richard-Qin-X	2026-08-13	36	-4853/+4505
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*	[CodeGen] Align pass manager ownership	Richard-Qin-X	2026-08-13	108	-2534/+2435
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*	[CodeGen] Split machine liveness components	Richard-Qin-X	2026-08-13	64	-2604/+3051
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*	[CodeGen] Split PHI elimination and two-address rewriting	Richard-Qin-X	2026-08-13	13	-1723/+1917
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*	[RISCV] Split the GlobalISel target components	Richard-Qin-X	2026-08-12	50	-6937/+7097
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*	[GlobalISel] Split the generic pipeline components	Richard-Qin-X	2026-08-12	24	-1633/+2003
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*	[RISCV] Consolidate instruction behavior in RISCVInstrInfo	Richard-Qin-X	2026-08-12	23	-347/+366
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*	[CodeGen] Add TargetInstrInfo ownership	Richard-Qin-X	2026-08-12	21	-54/+66
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*	[Tooling] Remove the duplicate assembly emitter	Richard-Qin-X	2026-08-12	7	-392/+0
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*	[Testing] Add the LLVM MIR RUN executor	Richard-Qin-X	2026-08-12	1	-0/+682
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*	[Tooling] Complete the LLVM MIR command-line contract	Richard-Qin-X	2026-08-12	21	-335/+620
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*	[Tooling] Adopt LLVM MIR command-line spellings	Richard-Qin-X	2026-08-12	14	-100/+202
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*	[CodeGen] Verify local physical live-ins	Richard-Qin-X	2026-08-12	2	-3/+103
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*	[CodeGen] Allow dynamic implicit operands on copies	Richard-Qin-X	2026-08-12	2	-1/+6
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*	[RISCV] Describe vector tuple registers	Richard-Qin-X	2026-08-12	3	-3/+100
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*	[RISCV] Describe vector physical registers	Richard-Qin-X	2026-08-12	2	-3/+89
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*	[clang-format] Format MIR sources	Richard-Qin-X	2026-08-12	3	-18/+15
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*	[MIR] Remove alternate layout and float APIs	Richard-Qin-X	2026-08-12	22	-122/+94
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*	[RISCV] Add Zba and Zbb instruction descriptions	Richard-Qin-X	2026-08-12	6	-8/+292
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*	[CodeGen] Allow narrow atomic RMW memory types	Richard-Qin-X	2026-08-12	2	-1/+26
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*	[RISCV] Make call-preserved masks optional	Richard-Qin-X	2026-08-12	2	-3/+7
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*	[RISCV] Make target memory operands optional	Richard-Qin-X	2026-08-12	3	-55/+15
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*	[CodeGen] Preserve variable-sized stack object offsets	Richard-Qin-X	2026-08-12	2	-6/+8
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*	[RISCV] Legalize G_PTR_ADD with s64 offsets	Richard-Qin-X	2026-08-12	2	-2/+29
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*	[RISCV] Legalize G_FRAME_INDEX for p0	Richard-Qin-X	2026-08-12	2	-0/+54
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*	[RISCV] Legalize G_VAARG	Richard-Qin-X	2026-08-12	4	-38/+288
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*	[RISCV] Accept symbolic low operands in loads and stores	Richard-Qin-X	2026-08-12	2	-15/+47
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*	[RISCV] Legalize llvm.va_copy	Richard-Qin-X	2026-08-12	5	-3/+200
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*	[RISCV] Allow frame indices in ADDI	Richard-Qin-X	2026-08-12	2	-5/+6
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*	[MIR] Create virtual registers referenced by live-ins	Richard-Qin-X	2026-08-12	4	-6/+57
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*	[CodeGen] Track reserved register defs precisely	Richard-Qin-X	2026-08-12	3	-12/+33
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*	[CodeGen] Test cloning unnamed functions	Richard-Qin-X	2026-08-12	1	-5/+5
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*	[RISCV] Model dynamic rounding-mode state	Richard-Qin-X	2026-08-12	2	-7/+65
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*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	5	-7/+129
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*	[MIR] Ignore empty YAML documents	Richard-Qin-X	2026-08-12	2	-16/+64
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