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* [RISCV] Generate complete Zcmp instruction definitionsRichard-Qin-X2026-08-286-44/+217
* [CodeGen] Add target machine registryRichard-Qin-X2026-08-2824-233/+735
* [CodeGen] Separate assembly emission ownershipRichard-Qin-X2026-08-2815-930/+1033
* [RISCV] Separate calling convention assignmentRichard-Qin-X2026-08-286-479/+566
* [CodeGen] Separate pass instrumentation ownershipRichard-Qin-X2026-08-287-612/+648
* [CodeGen] Remove pass instrumentation snapshotsRichard-Qin-X2026-08-282-104/+11
* [CodeGen] Centralize machine instruction erasureRichard-Qin-X2026-08-2830-474/+148
* [GlobalISel] Generate floating memory selectionRichard-Qin-X2026-08-279-159/+179
* [RISCV] Generate atomic RMW selectionRichard-Qin-X2026-08-273-95/+366
* [RISCV] Remove unused selector helpersRichard-Qin-X2026-08-271-80/+0
* [GlobalISel] Select each instruction onceRichard-Qin-X2026-08-273-93/+0
* [CodeGen] Remove machine action replayRichard-Qin-X2026-08-275-214/+16
* [CodeGen] Run machine optimizations onceRichard-Qin-X2026-08-2713-217/+21
* [CodeGen] Run scheduling transformations onceRichard-Qin-X2026-08-267-138/+30
* [CodeGen] Remove transactional register allocationRichard-Qin-X2026-08-269-174/+47
* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-264-57/+22
* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-266-78/+20
* [CodeGen] Centralize machine pass property validationRichard-Qin-X2026-08-2624-169/+0
* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-2610-27/+318
* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-2610-5/+667
* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-2610-43/+554
* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-264-0/+642
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-2516-46/+454
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-2511-4/+492
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-2510-6/+1167
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-254-0/+522
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-259-0/+392
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-246-1/+478
* [RISCV] Implement save and restore libcallsRichard-Qin-X2026-08-243-75/+347
* [CodeGen] Match LLVM callee-save live-insRichard-Qin-X2026-08-241-1/+1
* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-247-104/+102
* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-243-209/+290
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-2415-230/+393
* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-246-343/+179
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-2413-155/+164
* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-246-1/+359
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-2215-207/+392
* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-229-2/+85
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-2237-91/+1323
* [CodeGen] Match LLVM final verifier contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM finalization contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM late pseudo contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-195-270/+0
* [CodeGen] Match LLVM block placement contractRichard-Qin-X2026-08-191-6/+2
* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-197-469/+310
* [CodeGen] Match LLVM tail duplication contractRichard-Qin-X2026-08-191-9/+1
* [CodeGen] Match LLVM post-machine scheduler contractRichard-Qin-X2026-08-191-7/+1
* [CodeGen] Match LLVM post-RA pseudo expansion contractRichard-Qin-X2026-08-191-7/+1
* [CodeGen] Remove non-LLVM machine DCE placementsRichard-Qin-X2026-08-192-8/+2
* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-194-25/+1
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 12:09:48 +0000