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* Add fibonacci tests and fix bugsRichard Qin2026-03-181-2/+9
* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-181-0/+556
* Hazard unit and testsRichard Qin2026-03-181-0/+152
* refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
* Write Back stage unit and testsRichard Qin2026-03-181-0/+116
* docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-177-17/+595
* Execute Stage unit and testsRichard Qin2026-03-171-0/+114
* ID/EX Pipeline Register and testsRichard Qin2026-03-171-0/+174
* IF/ID RegFile and testsRichard Qin2026-03-171-0/+57
* Instruction Decoder Stage unit and testsRichard Qin2026-03-171-0/+142
* Instruction fetching stage unit and testRichard Qin2026-03-161-0/+60
* branch unit and testRichard Qin2026-03-162-0/+65
* fix naming problemsRichard Qin2026-03-163-39/+39
* Decoder unit and testRichard Qin2026-03-161-0/+390
* Register file unit and testRichard Qin2026-03-161-0/+60
* Add and test alu unitRichard Qin2026-03-152-0/+160
* initial commit: project architectureRichard Qin2026-03-156-0/+0
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 16:20:44 +0000