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* refactor: align RTL module names with filesRichard Qin2 days10-15/+15
* refactor: rename RTL source filesRichard Qin2 days8-0/+0
* refactor: reorganize RTL directory structureRichard Qin2 days27-394/+0
* checkpoint: preserve current RV64 CPU development stateRichard Qin2 days24-456/+6344
* refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-071-5/+5
* refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-074-66/+66
* feat(tlb): enhance TLB functionality with ASID-targeted flush and additional ...Richard Qin2026-04-071-1/+1
* feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-011-0/+378
* feat: Complete CSR/privileged/exception interrupt path and fill in strict acc...Richard Qin2026-04-0111-135/+410
* Trap Control unit and testsRichard Qin2026-03-191-0/+204
* CSR unit and testsRichard Qin2026-03-193-1/+547
* M/S/U Mode csr pakageRichard Qin2026-03-181-0/+110
* Add fibonacci tests and fix bugsRichard Qin2026-03-181-2/+9
* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-181-0/+556
* Hazard unit and testsRichard Qin2026-03-181-0/+152
* refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
* Write Back stage unit and testsRichard Qin2026-03-181-0/+116
* docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-177-17/+595
* Execute Stage unit and testsRichard Qin2026-03-171-0/+114
* ID/EX Pipeline Register and testsRichard Qin2026-03-171-0/+174
* IF/ID RegFile and testsRichard Qin2026-03-171-0/+57
* Instruction Decoder Stage unit and testsRichard Qin2026-03-171-0/+142
* Instruction fetching stage unit and testRichard Qin2026-03-161-0/+60
* branch unit and testRichard Qin2026-03-162-0/+65
* fix naming problemsRichard Qin2026-03-163-39/+39
* Decoder unit and testRichard Qin2026-03-161-0/+390
* Register file unit and testRichard Qin2026-03-161-0/+60
* Add and test alu unitRichard Qin2026-03-152-0/+160
* initial commit: project architectureRichard Qin2026-03-156-0/+0
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