| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | checkpoint: preserve current RV64 CPU development state | Richard Qin | 3 days | 1 | -15/+83 |
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| * | refactor: standardize interrupt signal naming across the codebase | Richard Qin | 2026-04-07 | 1 | -8/+8 |
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| * | refactor: standardize interrupt signal naming across the codebase | Richard Qin | 2026-04-07 | 1 | -8/+8 |
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| * | test(trap_ctrl): add store page fault unit test case | Richard Qin | 2026-03-31 | 1 | -2/+10 |
| | | | | | | | | | | Added a specific test scenario for Store Page Fault in tb/unit/tb_trap_ctrl.cc. - Defined EXC_STORE_PAGE_FAULT (15) constant. - Implemented a test case that asserts trap_store_page_fault and verifies mcause and mtval. - Improved clarity by renaming existing page fault test labels to LoadPageFault. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com> | ||||
| * | feat: Complete CSR/privileged/exception interrupt path and fill in strict ↵ | Richard Qin | 2026-04-01 | 1 | -0/+16 |
| | | | | | | | | | | | | | | | | | | acceptance tests - Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process - Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return - Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios - Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers - Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case - Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc. - Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite Verification: - Build passed - Full CTest passed (22/22) | ||||
| * | Trap Control unit and tests | Richard Qin | 2026-03-19 | 1 | -0/+192 |
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