| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | test(core): fix WB stage tests after naming and logic refactor | Richard Qin | 2026-03-17 | 1 | -5/+8 |
| * | Write Back stage unit and tests | Richard Qin | 2026-03-18 | 1 | -0/+115 |
| * | docs: Finalized Richard CPU RTL architectural and naming convention audit rep... | Richard Qin | 2026-03-17 | 5 | -3/+568 |
| * | Execute Stage unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+218 |
| * | ID/EX Pipeline Register and tests | Richard Qin | 2026-03-17 | 1 | -0/+171 |
| * | IF/ID RegFile and tests | Richard Qin | 2026-03-17 | 1 | -0/+127 |
| * | Instruction Decoder Stage unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+192 |
| * | Instruction fetching stage unit and test | Richard Qin | 2026-03-16 | 1 | -0/+111 |
| * | branch unit and test | Richard Qin | 2026-03-16 | 1 | -0/+100 |
| * | format output | Richard Qin | 2026-03-16 | 3 | -13/+20 |
| * | expand tests and format output | Richard Qin | 2026-03-16 | 3 | -9/+124 |
| * | fix naming problems | Richard Qin | 2026-03-16 | 3 | -37/+37 |
| * | Decoder unit and test | Richard Qin | 2026-03-16 | 1 | -0/+298 |
| * | Register file unit and test | Richard Qin | 2026-03-16 | 1 | -0/+99 |
| * | License | Richard Qin | 2026-03-15 | 1 | -0/+17 |
| * | Add and test alu unit | Richard Qin | 2026-03-15 | 1 | -0/+67 |
| * | initial commit: project architecture | Richard Qin | 2026-03-15 | 1 | -0/+0 |
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