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* test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
| | | | | | | | | - Renamed `wb_reg_write_data` to `wb_rd_wdata` in all assertions to match the updated module ports. - Renamed `wb_reg_write_addr` to `wb_rd_addr` in all assertions. - Initialized the new `mem_wb_pc_plus_4` input in the testbench setup to correctly test the JAL/JALR datapath. - Added assertions to explicitly test that `wb_reg_write_en` and `csr_req` are gated when an exception occurs. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Write Back stage unit and testsRichard Qin2026-03-181-0/+115
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* docs: Finalized Richard CPU RTL architectural and naming convention audit ↵Richard Qin2026-03-175-3/+568
| | | | | | | | report. No source code changes were made; this branch serves as the finalized state for the provided audit. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Execute Stage unit and testsRichard Qin2026-03-171-0/+218
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* ID/EX Pipeline Register and testsRichard Qin2026-03-171-0/+171
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* IF/ID RegFile and testsRichard Qin2026-03-171-0/+127
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* Instruction Decoder Stage unit and testsRichard Qin2026-03-171-0/+192
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* Instruction fetching stage unit and testRichard Qin2026-03-161-0/+111
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* branch unit and testRichard Qin2026-03-161-0/+100
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* format outputRichard Qin2026-03-163-13/+20
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* expand tests and format outputRichard Qin2026-03-163-9/+124
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* fix naming problemsRichard Qin2026-03-163-37/+37
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* Decoder unit and testRichard Qin2026-03-161-0/+298
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* Register file unit and testRichard Qin2026-03-161-0/+99
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* LicenseRichard Qin2026-03-151-0/+17
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* Add and test alu unitRichard Qin2026-03-151-0/+67
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* initial commit: project architectureRichard Qin2026-03-151-0/+0
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 22:25:44 +0000