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* checkpoint: preserve current RV64 CPU development stateRichard Qin3 days9-415/+985
* refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-072-22/+22
* refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-071-8/+8
* feat(tlb): enhance TLB functionality with ASID-targeted flush and additional ...Richard Qin2026-04-071-0/+63
* feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-011-0/+418
* test(trap_ctrl): add store page fault unit test caseRichard Qin2026-03-311-2/+10
* feat: Complete CSR/privileged/exception interrupt path and fill in strict acc...Richard Qin2026-04-016-59/+434
* Trap Control unit and testsRichard Qin2026-03-191-0/+192
* CSR unit and testsRichard Qin2026-03-191-0/+335
* Add fibonacci tests and fix bugsRichard Qin2026-03-181-6/+7
* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-182-0/+24
* Hazard unit and testsRichard Qin2026-03-181-0/+285
* test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
* Write Back stage unit and testsRichard Qin2026-03-181-0/+115
* docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-175-3/+568
* Execute Stage unit and testsRichard Qin2026-03-171-0/+218
* ID/EX Pipeline Register and testsRichard Qin2026-03-171-0/+171
* IF/ID RegFile and testsRichard Qin2026-03-171-0/+127
* Instruction Decoder Stage unit and testsRichard Qin2026-03-171-0/+192
* Instruction fetching stage unit and testRichard Qin2026-03-161-0/+111
* branch unit and testRichard Qin2026-03-161-0/+100
* format outputRichard Qin2026-03-163-13/+20
* expand tests and format outputRichard Qin2026-03-163-9/+124
* fix naming problemsRichard Qin2026-03-163-37/+37
* Decoder unit and testRichard Qin2026-03-161-0/+298
* Register file unit and testRichard Qin2026-03-161-0/+99
* LicenseRichard Qin2026-03-151-0/+17
* Add and test alu unitRichard Qin2026-03-151-0/+67
* initial commit: project architectureRichard Qin2026-03-151-0/+0
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