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* feat(tlb): enhance TLB functionality with ASID-targeted flush and additional ...Richard Qin2026-04-071-0/+63
* feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-012-0/+427
* feat(compliance): implement ACT4 strict compliance flow with ELF runnerRichard Qin2026-04-013-14/+439
* test(trap_ctrl): add store page fault unit test caseRichard Qin2026-03-311-2/+10
* feat: Complete CSR/privileged/exception interrupt path and fill in strict acc...Richard Qin2026-04-018-66/+859
* Trap Control unit and testsRichard Qin2026-03-192-0/+202
* CSR unit and testsRichard Qin2026-03-192-9/+346
* Add fibonacci tests and fix bugsRichard Qin2026-03-182-6/+68
* fixed vm_trace bugRichard Qin2026-03-181-6/+6
* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-184-8/+696
* Hazard unit and testsRichard Qin2026-03-182-0/+294
* test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
* Write Back stage unit and testsRichard Qin2026-03-182-0/+124
* docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-176-3/+595
* Execute Stage unit and testsRichard Qin2026-03-172-0/+229
* ID/EX Pipeline Register and testsRichard Qin2026-03-172-0/+180
* IF/ID RegFile and testsRichard Qin2026-03-172-0/+136
* Instruction Decoder Stage unit and testsRichard Qin2026-03-172-0/+203
* Instruction fetching stage unit and testRichard Qin2026-03-162-0/+120
* branch unit and testRichard Qin2026-03-162-0/+109
* format outputRichard Qin2026-03-163-13/+20
* expand tests and format outputRichard Qin2026-03-163-9/+124
* fix naming problemsRichard Qin2026-03-163-37/+37
* Decoder unit and testRichard Qin2026-03-162-9/+307
* Register file unit and testRichard Qin2026-03-162-13/+112
* LicenseRichard Qin2026-03-151-0/+17
* Add and test alu unitRichard Qin2026-03-152-8/+75
* initial commit: project architectureRichard Qin2026-03-157-0/+135
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