| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | IF/ID RegFile and tests | Richard Qin | 2026-03-17 | 2 | -0/+136 |
| * | Instruction Decoder Stage unit and tests | Richard Qin | 2026-03-17 | 2 | -0/+203 |
| * | Instruction fetching stage unit and test | Richard Qin | 2026-03-16 | 2 | -0/+120 |
| * | branch unit and test | Richard Qin | 2026-03-16 | 2 | -0/+109 |
| * | format output | Richard Qin | 2026-03-16 | 3 | -13/+20 |
| * | expand tests and format output | Richard Qin | 2026-03-16 | 3 | -9/+124 |
| * | fix naming problems | Richard Qin | 2026-03-16 | 3 | -37/+37 |
| * | Decoder unit and test | Richard Qin | 2026-03-16 | 2 | -9/+307 |
| * | Register file unit and test | Richard Qin | 2026-03-16 | 2 | -13/+112 |
| * | License | Richard Qin | 2026-03-15 | 1 | -0/+17 |
| * | Add and test alu unit | Richard Qin | 2026-03-15 | 2 | -8/+75 |
| * | initial commit: project architecture | Richard Qin | 2026-03-15 | 7 | -0/+135 |
