1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
|
// SPDX-License-Identifier: GPL-3.0-or-later
#include "rcc/Target/RISCV/RISCVTarget.h"
#include "rcc/CodeGen/GenericOpcodes.h"
#include <algorithm>
#include <cstddef>
#include <cstdint>
#include <iostream>
#include <ranges>
#include <string_view>
namespace {
class TestContext final {
public:
void expect(bool Condition, std::string_view Message) {
if (Condition)
return;
std::cerr << Message << '\n';
++FailureCount;
}
[[nodiscard]] int result() const noexcept {
return FailureCount == 0 ? 0 : 1;
}
private:
int FailureCount = 0;
};
[[nodiscard]] rcc::PhysicalRegister registerID(rcc::riscv::PhysicalRegisterID ID) {
const auto Register = rcc::riscv::physicalRegister(ID);
if (!Register)
std::terminate();
return *Register;
}
void testRegisterFacts(TestContext &Context) {
auto Registers = rcc::riscv::createRegisterInfo();
Context.expect(Registers.has_value(), "RV64GC register description must be valid");
if (!Registers)
return;
const rcc::PhysicalRegister X0 = registerID(rcc::riscv::PhysicalRegisterID::X0);
const rcc::PhysicalRegister X2 = registerID(rcc::riscv::PhysicalRegisterID::X2);
const rcc::PhysicalRegister X5 = registerID(rcc::riscv::PhysicalRegisterID::X5);
const rcc::PhysicalRegister X8 = registerID(rcc::riscv::PhysicalRegisterID::X8);
const rcc::PhysicalRegister F31 = registerID(rcc::riscv::PhysicalRegisterID::F31);
Context.expect(
Registers->physicalRegisters().size() == 64 && Registers->registerUnits().size() == 64 &&
Registers->registerClasses().size() == 8 && Registers->registerBanks().size() == 2,
"RV64GC must expose the complete scalar, compressed, and restricted register classes");
Context.expect(Registers->physicalRegister("x0") != nullptr &&
Registers->physicalRegister("zero") == nullptr &&
Registers->physicalRegisterByAlternativeName("ZERO") != nullptr &&
Registers->physicalRegisterByAlternativeName("zero")->Reg == X0 &&
Registers->physicalRegisterByAlternativeName("Sp") != nullptr &&
Registers->physicalRegisterByAlternativeName("sp")->Reg == X2 &&
Registers->physicalRegisterMIRName(X8) == "x8",
"canonical MIR names and case-insensitive ABI aliases must use separate lookups");
Context.expect(
Registers->isReservedRegister(X0) && Registers->isReservedRegister(X2) &&
!Registers->isReservedRegister(X5),
"zero, stack, global, and thread register constraints must be recorded statically");
Context.expect(Registers->physicalRegister(F31) != nullptr &&
Registers->physicalRegister(F31)->Encoding == 31,
"floating register physical IDs must remain distinct from their ISA encodings");
const auto *GPR = Registers->registerClass("gpr");
Context.expect(
GPR != nullptr && std::ranges::find(GPR->AllocationOrder, X0) == GPR->AllocationOrder.end() &&
std::ranges::find(GPR->AllocationOrder, X2) == GPR->AllocationOrder.end() &&
std::ranges::find(GPR->AllocationOrder, X5) != GPR->AllocationOrder.end(),
"the general-register allocation order must exclude statically reserved registers");
Context.expect(Registers->registerClass("gpr_nx0") != nullptr &&
Registers->registerClass("gpr_nx0_nx2") != nullptr,
"compressed instructions must have explicit nonzero register classes");
}
void testABIAndDebugFacts(TestContext &Context) {
const rcc::PhysicalRegister X1 = registerID(rcc::riscv::PhysicalRegisterID::X1);
const rcc::PhysicalRegister X10 = registerID(rcc::riscv::PhysicalRegisterID::X10);
const rcc::PhysicalRegister F8 = registerID(rcc::riscv::PhysicalRegisterID::F8);
const rcc::PhysicalRegister F10 = registerID(rcc::riscv::PhysicalRegisterID::F10);
const rcc::PhysicalRegister F31 = registerID(rcc::riscv::PhysicalRegisterID::F31);
const auto Mask = rcc::riscv::createCallPreservedMask();
Context.expect(
Mask != nullptr && Mask->preserves(X1) && Mask->preserves(F8) && Mask->clobbers(X10) &&
Mask->clobbers(F10),
"LP64D preserved-mask facts must distinguish saved and caller-clobbered registers");
auto MIRText = rcc::riscv::createMIRTextInfo();
Context.expect(MIRText.has_value(), "RV64GC MIR text facts must be valid");
if (!MIRText)
return;
Context.expect(MIRText->registerMasks().size() == 1 &&
MIRText->registerMasks().front().Name == "csr_ilp32d_lp64d",
"RV64GC must expose its named LP64D call-preserved mask");
Context.expect(MIRText->directOperandFlagMask() == 31 &&
MIRText->directOperandFlag("riscv-call") == 1,
"RV64GC MIR target flags must expose the canonical direct-call spelling");
Context.expect(MIRText->dwarfRegister(X1) == 1,
"the return-address register must retain its DWARF register number");
Context.expect(MIRText->physicalRegister(63) == F31,
"the final floating register DWARF number must map to f31");
const auto Conventions = rcc::riscv::callingConventions();
const auto *LP64D = rcc::riscv::callingConvention(rcc::riscv::CallingConvention::LP64D);
Context.expect(
Conventions.size() == 1 && LP64D != nullptr && LP64D->Name == "lp64d" &&
LP64D->IntegerArgumentRegisters.size() == 8 &&
LP64D->FloatingArgumentRegisters.size() == 8 &&
LP64D->IntegerReturnRegisters.size() == 2 && LP64D->FloatingReturnRegisters.size() == 2 &&
LP64D->StackAlignmentBytes == 16 && LP64D->StackArgumentAlignmentBytes == 16 &&
LP64D->SupportsVarArgs && LP64D->SupportsTailCalls &&
LP64D->PreservedMaskName == "CSR_ILP32D_LP64D",
"LP64D calling-convention tables must expose register, stack, and tail-call facts");
}
void testInstructionFacts(TestContext &Context) {
constexpr std::size_t TargetInstructionCount =
static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::G_SLLW) -
static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::LUI) + 1U;
auto Target = rcc::riscv::createTargetDescription();
Context.expect(Target.has_value(), "RV64GC target description must be structurally valid");
if (!Target) {
std::cerr << "target construction error: " << Target.error().message() << '\n';
return;
}
const auto *Addi = Target->instructionDescriptor(
rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::ADDI)));
const auto *Load = Target->instructionDescriptor(
rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::LD)));
const auto *Branch = Target->instructionDescriptor(
rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::BEQ)));
const auto *Floating = Target->instructionDescriptor(
rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::FADD_S)));
const auto *Atomic = Target->instructionDescriptor(
rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::LR_W)));
const auto *Compressed = Target->instructionDescriptor(rcc::Opcode::fromValue(
static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::C_ADDI16SP)));
const auto *GenericAdd = Target->instructionDescriptor(rcc::opcode(rcc::GenericOpcode::G_ADD));
const auto *PseudoCall = Target->instructionDescriptor(rcc::Opcode::fromValue(
static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::PseudoCALL)));
const auto *Assembly = rcc::riscv::assemblyInstruction(
rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::ADDI)));
const auto *FenceAssembly = rcc::riscv::assemblyInstruction(
rcc::Opcode::fromValue(static_cast<std::uint32_t>(rcc::riscv::InstructionOpcode::FENCE_I)));
Context.expect(
Target->instructions().descriptors().size() ==
TargetInstructionCount + rcc::genericInstructionDescriptors().size() &&
Addi != nullptr && Addi->Name == "ADDI" && Addi->NumExplicitDefs == 1 &&
Addi->Operands.size() == 3 && Addi->Operands.back().ImmediatePredicate &&
Load != nullptr && Load->Flags.has(rcc::InstructionFlag::MayLoad) &&
Load->RequiresMemoryOperands && Branch != nullptr &&
Branch->Flags.has(rcc::InstructionFlag::Terminator) &&
Branch->Flags.has(rcc::InstructionFlag::Branch) && Floating != nullptr &&
Floating->Operands.size() == 4 && Floating->Operands.back().ImmediatePredicate &&
Atomic != nullptr && Atomic->Flags.has(rcc::InstructionFlag::MayLoad) &&
Atomic->RequiresMemoryOperands && Compressed != nullptr &&
Compressed->ImplicitDefs.size() == 1 && Compressed->ImplicitUses.size() == 1 &&
GenericAdd != nullptr && GenericAdd->Flags.has(rcc::InstructionFlag::Generic) &&
PseudoCall != nullptr && PseudoCall->Flags.has(rcc::InstructionFlag::Pseudo) &&
PseudoCall->Flags.has(rcc::InstructionFlag::Call) &&
rcc::riscv::assemblyInstruction(PseudoCall->InstructionOpcode) == nullptr &&
Assembly != nullptr && Assembly->Mnemonic == "addi" &&
Assembly->Format == rcc::AssemblyFormatID::fromValue(static_cast<std::uint32_t>(
rcc::riscv::AssemblyFormat::RD_RS1_IMM)),
"generated instruction and assembly descriptors must drive the formal RV64GC target");
const auto Schedules = rcc::riscv::schedulingClasses();
const auto Encodings = rcc::riscv::encodingCategories();
const auto Formats = rcc::riscv::assemblyFormats();
Context.expect(Schedules.size() == 15 && Encodings.size() == 10 && Formats.size() == 34 &&
rcc::riscv::assemblyInstructions().size() == 195 && FenceAssembly != nullptr &&
FenceAssembly->Mnemonic == "fence.i" &&
std::ranges::any_of(Schedules,
[](const rcc::riscv::SchedulingClassInfo &Class) {
return Class.Name == "load" && Class.MicroOps == 1 &&
Class.Latency == 3;
}) &&
std::ranges::any_of(Encodings,
[](const rcc::riscv::EncodingCategoryInfo &Category) {
return Category.Name == "i" && Category.SizeInBytes == 4;
}) &&
std::ranges::any_of(Formats,
[](const rcc::riscv::AssemblyFormatInfo &Format) {
return Format.Name == "rd-rs1-imm";
}),
"generated scheduling, encoding, and assembly tables must preserve target facts");
}
} // namespace
int main() {
TestContext Context;
testRegisterFacts(Context);
testABIAndDebugFacts(Context);
testInstructionFacts(Context);
return Context.result();
}
|
