blob: f16aa1467e5f8c8f1d323557c8e6b2c4d80b59f4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
cmake_minimum_required(VERSION 3.20)
if(POLICY CMP0144)
cmake_policy(SET CMP0144 NEW)
endif()
project(rv64cpu
VERSION 0.1.0
DESCRIPTION "RV64 RISC-V processor core written in SystemVerilog"
LANGUAGES CXX
)
set(CMAKE_CXX_STANDARD 17)
set(CMAKE_CXX_STANDARD_REQUIRED ON)
set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
option(ENABLE_TRACE "Enable VCD waveform tracing" OFF)
option(ENABLE_COVERAGE "Enable RTL code coverage" OFF)
find_package(verilator REQUIRED HINTS $ENV{VERILATOR_ROOT})
message(STATUS "Found Verilator: ${verilator_DIR}")
set(VERILATOR_COMMON_FLAGS
--sv
-Wall
-Wno-DECLFILENAME
-Wno-UNUSED
--x-initial unique
--x-assign unique
)
if(ENABLE_TRACE)
list(APPEND VERILATOR_COMMON_FLAGS --trace)
add_compile_definitions(VM_TRACE=1)
endif()
if(ENABLE_COVERAGE)
list(APPEND VERILATOR_COMMON_FLAGS --coverage)
endif()
include(${CMAKE_SOURCE_DIR}/cmake/verilator.cmake)
add_subdirectory(rtl)
message(STATUS "")
message(STATUS "RV64CPU configuration")
message(STATUS " Trace: ${ENABLE_TRACE}")
message(STATUS " Coverage: ${ENABLE_COVERAGE}")
message(STATUS " RTL files: ${RV64CPU_RTL_SOURCE_COUNT}")
message(STATUS "")
|
