1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
// Richard CPU
// Copyright (C) 2026 Richard Qin
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
// File path: rtl/core/mem_wb_reg.sv
// Description: MEM/WB pipeline stage register (Memory Access to Write Back)
// Passes the final computation results, memory read data, and write-back control signals to the write-back stage
module mem_wb_reg
import rv64_pkg::*;
(
input logic clk,
input logic rst,
// -----------------------
// Control Signals from Hazard Unit
input logic stall_en,
input logic flush_en,
// -----------------------
// Inputs from MEM stage
// -----------------------
// Data and addresses
input logic [XLEN-1:0] mem_pc,
input logic [XLEN-1:0] mem_alu_result,
input logic [XLEN-1:0] mem_mem_rdata,
// Write back control
input logic mem_reg_write_en,
input logic [4:0] mem_rd_addr,
input logic [1:0] mem_wb_sel,
// CSR & System
input logic mem_is_csr,
input logic [2:0] mem_csr_op,
input logic [XLEN-1:0] mem_rs1_rdata,
input logic [4:0] mem_rs1_addr,
input logic [XLEN-1:0] mem_imm,
input logic mem_illegal_instr,
input logic mem_is_ecall,
input logic mem_is_ebreak,
input logic mem_is_mret,
input logic mem_is_sret,
// -----------------------
// Outputs to WB Stage
// -----------------------
// Data and address
output logic [XLEN-1:0] wb_pc,
output logic [XLEN-1:0] wb_alu_result,
output logic [XLEN-1:0] wb_mem_rdata,
// Write back control
output logic wb_reg_write_en,
output logic [4:0] wb_rd_addr,
output logic [1:0] wb_wb_sel,
// CSR & System
output logic wb_is_csr,
output logic [2:0] wb_csr_op,
output logic [XLEN-1:0] wb_rs1_rdata,
output logic [4:0] wb_rs1_addr,
output logic [XLEN-1:0] wb_imm,
output logic wb_illegal_instr,
output logic wb_is_ecall,
output logic wb_is_ebreak,
output logic wb_is_mret,
output logic wb_is_sret
);
// Sequential Logic: State Update
always_ff @(posedge clk) begin
if (rst) begin
wb_pc <= '0;
wb_alu_result <= '0;
wb_mem_rdata <= '0;
wb_reg_write_en <= '0;
wb_rd_addr <= '0;
wb_wb_sel <= '0;
wb_is_csr <= '0;
wb_csr_op <= '0;
wb_rs1_rdata <= '0;
wb_rs1_addr <= '0;
wb_imm <= '0;
wb_illegal_instr <= '0;
wb_is_ecall <= '0;
wb_is_ebreak <= '0;
wb_is_mret <= '0;
wb_is_sret <= '0;
end else if (flush_en) begin
// Target specific control signals to clear. Leave datapath elements intact
// to avoid extreme power consumption from massive flip-flop state changes array.
wb_reg_write_en <= '0;
wb_is_csr <= '0;
wb_illegal_instr <= '0;
wb_is_ecall <= '0;
wb_is_ebreak <= '0;
wb_is_mret <= '0;
wb_is_sret <= '0;
end else if (!stall_en) begin
wb_pc <= mem_pc;
wb_alu_result <= mem_alu_result;
wb_mem_rdata <= mem_mem_rdata;
wb_reg_write_en <= mem_reg_write_en;
wb_rd_addr <= mem_rd_addr;
wb_wb_sel <= mem_wb_sel;
wb_is_csr <= mem_is_csr;
wb_csr_op <= mem_csr_op;
wb_rs1_rdata <= mem_rs1_rdata;
wb_rs1_addr <= mem_rs1_addr;
wb_imm <= mem_imm;
wb_illegal_instr <= mem_illegal_instr;
wb_is_ecall <= mem_is_ecall;
wb_is_ebreak <= mem_is_ebreak;
wb_is_mret <= mem_is_mret;
wb_is_sret <= mem_is_sret;
end
end
endmodule
|
