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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-09-28 01:19:45 +0800 |
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| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-09-28 01:19:45 +0800 |
| commit | 1425c561f3ee0b3085cea63fc364eb53bfb29757 (patch) | |
| tree | 3c772591da3395134b23bb891a11f200f7e7f003 | |
| parent | e41ece62eface57c61438eb2e16ccfcbdbafedc0 (diff) | |
| download | rhomepage-1425c561f3ee0b3085cea63fc364eb53bfb29757.tar.gz rhomepage-1425c561f3ee0b3085cea63fc364eb53bfb29757.tar.xz | |
Update project descriptions
| -rw-r--r-- | content/projects/_index.md | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/content/projects/_index.md b/content/projects/_index.md index 74f1a0e..d2360cf 100644 --- a/content/projects/_index.md +++ b/content/projects/_index.md @@ -13,3 +13,25 @@ A document-first personal website that publishes each article as readable HTML a - Technology: Hugo, HTML, CSS, POSIX shell - License: GPL-3.0-or-later - [source](https://git.richardqin.org/rhomepage) + +## rcc + +An optimizing compiler for SysY, a C subset, targeting RISC-V 64GC. It uses a QBE-inspired SSA architecture with a substantial optimization pipeline: the mid-end includes mem2reg, GVN, GCM, LICM, SCCP, strength reduction, inlining, and DCE, while the RISC-V backend includes instruction selection, liveness analysis, spilling, register allocation, and peephole optimization. + +- Technology: C++, CMake, RISC-V 64GC +- [repository](https://git.richardqin.org/rcc/) + +## RUCDSA + +Coursework for the Renmin University of China Data Structure and Algorithm course, including C implementations and laboratory exercises. + +- Technology: C +- License: GPL-2.0 +- [repository](https://git.richardqin.org/RUCDSA/) + +## datalab2026 + +An RUC ICS DataLab implementation and test workspace covering binary representation, bitwise operations, and IEEE-754 floating-point manipulation. + +- Technology: C, Python, Make +- [repository](https://git.richardqin.org/datalab2026/) |