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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-05-02 23:31:46 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-05-02 23:31:46 +0800 |
| commit | 6907a90418ba856ff9331e6b4ba5d26b76034c2d (patch) | |
| tree | 420223afa8d8c9f4e0fab945ff01fea58a7d219a /na/arch/riscv/module.mk | |
| parent | 1146a45ccbbbf514787eba6082e7acbbbe8e81b8 (diff) | |
| download | lume-6907a90418ba856ff9331e6b4ba5d26b76034c2d.tar.gz lume-6907a90418ba856ff9331e6b4ba5d26b76034c2d.tar.xz | |
feat: add RISC-V configuration and memory management enhancements
Co-authored-by: Copilot <copilot@github.com>
Diffstat (limited to 'na/arch/riscv/module.mk')
| -rw-r--r-- | na/arch/riscv/module.mk | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/na/arch/riscv/module.mk b/na/arch/riscv/module.mk index 154ae77..9635fea 100644 --- a/na/arch/riscv/module.mk +++ b/na/arch/riscv/module.mk @@ -1,5 +1,8 @@ # arch/riscv/module.mk SRCS_CC += arch/riscv/mm/pmap.cc +SRCS_CC += arch/riscv/config.cc +SRCS_CC += arch/riscv/trap/trap_md.cc +SRCS_CC += arch/riscv/lib/random.cc SRCS_S += arch/riscv/boot/entry.S SRCS_S += arch/riscv/trap/swtch.S SRCS_S += arch/riscv/trap/trap_vector.S |