| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
| |
Archive the deprecated implementation under lume-legacy, make the new kernel the default root-level build, and update repository entry points without changing kernel behavior.
|
| |
|
|
| |
Rewrote the README based on the actual project.
|
| | |
|
| | |
|
| | |
|
| |
|
|
|
|
|
|
|
|
| |
Implement the initial mechanism for handling traps and exceptions in Supervisor Mode.
Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point.
Implemented assembly code for saving and restoring the Trap Context (register state).
Provides the foundational framework necessary for future Timer Interrupts and System Calls.
|
|
|
feat: Initial bare-metal RISC-V boot with UART
|