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* dev(device): implement VirtIORichard Qin2026-01-016-3/+133
| | | | See dev log for detail
* dev: PILC implementationRichard Qin2025-12-311-0/+17
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* dev:Refactor Memory Management and Process ManagementRichard Qin2025-12-3112-90/+169
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* dev(spinlock): refactoring the implementation of locksRichard Qin2025-12-302-15/+61
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* dev(pmm.h): refactor header fileRichard Qin2025-12-301-4/+44
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* feat(types): defined a type aliasRichard Qin2025-12-301-15/+20
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* feat(user): add user-space build system and init process to test fork/waitRichard Qin2025-12-282-1/+32
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* feat(syscall): Implement syscall dispatch and process lifecycle ↵Richard Qin2025-12-284-2/+69
| | | | (exit/wait/sleep)
* feat: Implement the first user program of the lume OSRichard Qin2025-12-275-16/+33
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* feat: Encapsulates the low-level hardware details of the RISC-V ↵Richard Qin2025-12-251-0/+400
| | | | | | architecture, providing interfaces for the rest of the kernel to operate CPU registers and manage memory Copied from the xv-6 source code.
* feat: add preemptive scheduling, SBI timer support and FDT parser.Richard Qin2025-12-132-1/+10
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* feat:Cooperative MultitaskingRichard Qin2025-12-112-0/+62
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* feat: Add initial Supervisor Mode Trap HandlerRichard Qin2025-12-103-1/+55
| | | | | | | | | | Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls.
* feat: Initial PMM implementationRichard Qin2025-12-092-0/+34
| | | | | | Introduce the foundational Physical Memory Manager (PMM) and restructure the project for modularity. Implemented basic PMM and related memory management headers (mm/pmm.h, mm/vm.h). Updated Makefile and build process to support new modular structure.
* The start of the project -- A MicroDOSRichard Qin2025-12-082-0/+21
feat: Initial bare-metal RISC-V boot with UART