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* refactor: promote new architecture to repository rootRichard Qin2026-07-1029-6868/+0
| | | | Archive the deprecated implementation under lume-legacy, make the new kernel the default root-level build, and update repository entry points without changing kernel behavior.
* feat: establish bootable new architecture checkpointRichard Qin2026-07-1025-331/+4692
| | | | Replace the compressed boot path with a relocatable higher-half RISC-V entry, expand memory and SMP support, and add the driver, TTY, VFS, exec, signal, syscall, initramfs, and self-test infrastructure needed for a bootable kernel checkpoint.
* feat: update module.mk files to include additional source files for various ↵Richard Qin2026-05-131-0/+14
| | | | subsystems
* feat: reorganize kernel_main initialization sequence and add syscall ↵Richard Qin2026-05-131-99/+153
| | | | initialization
* feat: implement user-kernel memory copy functions with validationRichard Qin2026-05-131-0/+67
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* feat: implement PID allocator with bitmap-based allocationRichard Qin2026-05-131-0/+61
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* feat: implement process control system calls (exit, getpid, gettid, ↵Richard Qin2026-05-131-0/+143
| | | | sched_yield, wait4)
* feat: implement memory management system calls (brk, mmap, munmap, mprotect)Richard Qin2026-05-131-0/+172
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* feat: implement sys_uname for system information retrievalRichard Qin2026-05-131-0/+49
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* feat: implement syscall dispatcher and initialization for system callsRichard Qin2026-05-131-0/+99
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* feat: implement O1RunQueue and RunQueue classes for task schedulingRichard Qin2026-05-131-0/+115
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* feat: implement task management for kernel threadsRichard Qin2026-05-131-0/+399
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* feat: implement WaitQueue class for blocking synchronizationRichard Qin2026-05-131-0/+97
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* feat: implement O(1) Priority Bitmap Scheduling Class and Scheduler CoreRichard Qin2026-05-132-0/+473
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* feat: implement MI Timer Subsystem with initialization and tick handlingRichard Qin2026-05-131-0/+44
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* feat: add signal subsystem interface and Linux-compatible signal numbersRichard Qin2026-05-131-1/+1
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* feat: implement machine-independent trap handling with dispatcher and statisticsRichard Qin2026-05-131-0/+194
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* feat: implement IRQ Manager with dynamic interrupt dispatch and atomic ↵Richard Qin2026-05-131-0/+106
| | | | handler registration
* feat: add boot parameters management with initialization and access functionsRichard Qin2026-05-131-0/+45
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* feat: replace panic.h with klog.h for improved logging in multiple filesRichard Qin2026-05-022-2/+2
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* feat: enhance kernel initialization with FDT parsing and self-test integrationRichard Qin2026-04-211-22/+41
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* feat: refactor Spinlock implementation to use atomic operations for lock ↵Richard Qin2026-04-212-6/+7
| | | | management
* feat: add features header and frame descriptor implementationRichard Qin2026-04-211-1/+2
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* feat: add initial RISC-V architecture support and core kernel functionalityRichard Qin2026-04-175-0/+354
- Implement MMU hardware primitives for RISC-V SV39 in mmu.h - Create trap vector control primitives in trap.h - Define trap frame structure for RISC-V in trapframe.h - Add assembly routines for context switching in swtch.S - Implement trap vector entry/exit in trap_vector.S - Introduce basic error number definitions in errno.h - Provide placement new/delete operators in new.h - Define kernel panic handler in panic.h and implement in panic.cc - Establish basic type definitions in types.h - Create the kernel main entry point in main.cc with global initialization - Add synchronization primitives using spinlocks in spinlock.h and spinlock.cc - Define per-CPU state tracking for interrupts in cpu_state.h - Create a linker script for the kernel in linker.ld - Update module makefiles for kernel and library components