refactor: align RTL module names with files

10 files changed, 15 insertions, 15 deletions

diff --git a/rv64cpu/rtl/core/execute/instruction_decoder.sv b/rv64cpu/rtl/core/execute/instruction_decoder.sv
index c39a637..14d9559 100644
--- a/rv64cpu/rtl/core/execute/instruction_decoder.sv
+++ b/rv64cpu/rtl/core/execute/instruction_decoder.sv
@@ -19,7 +19,7 @@
 //              Translates 32-bit instructions into control signals for the pipeline.
 //              C is handled by the IF-stage decompressor before this decoder.
 
-module decoder
+module instruction_decoder
     import rv64_pkg::*;
 (
     input  logic [31:0]       instr,          // 32-bit instruction
diff --git a/rv64cpu/rtl/core/execute/integer_alu.sv b/rv64cpu/rtl/core/execute/integer_alu.sv
index 08635ce..833f902 100644
--- a/rv64cpu/rtl/core/execute/integer_alu.sv
+++ b/rv64cpu/rtl/core/execute/integer_alu.sv
@@ -17,7 +17,7 @@
 // File path: rtl/core/alu.sv
 // Description: 64-bit Arithmetic Logic Unit (ALU)
 
-module alu
+module integer_alu
     import rv64_pkg::*;
 (
     input  alu_op_t          alu_op,     // ALU operation select (from decoder)
diff --git a/rv64cpu/rtl/core/fpu/fpu.sv b/rv64cpu/rtl/core/fpu/fpu.sv
index a1962e1..9e9494d 100644
--- a/rv64cpu/rtl/core/fpu/fpu.sv
+++ b/rv64cpu/rtl/core/fpu/fpu.sv
@@ -4,7 +4,7 @@
 // File path: rtl/core/fpu/fpu_unit.sv
 // Description: RV64F/RV64D floating-point execution unit.
 
-module fpu_unit
+module fpu
     import rv64_pkg::*;
 (
     input  fp_op_t            fp_op,
diff --git a/rv64cpu/rtl/core/mmu/mmu.sv b/rv64cpu/rtl/core/mmu/mmu.sv
index 169bf81..60c4afa 100644
--- a/rv64cpu/rtl/core/mmu/mmu.sv
+++ b/rv64cpu/rtl/core/mmu/mmu.sv
@@ -17,7 +17,7 @@
 // File path: rtl/core/mmu/mmu_top.sv
 // Description: MMU top-level integrating iTLB + dTLB + shared PTW
 
-module mmu_top
+module mmu
 	import rv64_pkg::*;
 #(
 	parameter int ITLB_ENTRIES = 16,
diff --git a/rv64cpu/rtl/core/pipeline/ex_stage.sv b/rv64cpu/rtl/core/pipeline/ex_stage.sv
index 287bfd7..2758ffc 100644
--- a/rv64cpu/rtl/core/pipeline/ex_stage.sv
+++ b/rv64cpu/rtl/core/pipeline/ex_stage.sv
@@ -88,7 +88,7 @@ module ex_stage
 
     // --------------
     // Instantiate the core computing engine ALU
-    alu alu_inst (
+    integer_alu alu_inst (
         .alu_op         (ex_alu_op),
         .operand_a      (alu_operand_a),
         .operand_b      (alu_operand_b),
diff --git a/rv64cpu/rtl/core/pipeline/id_stage.sv b/rv64cpu/rtl/core/pipeline/id_stage.sv
index 9003b42..1cf447a 100644
--- a/rv64cpu/rtl/core/pipeline/id_stage.sv
+++ b/rv64cpu/rtl/core/pipeline/id_stage.sv
@@ -108,7 +108,7 @@ module id_stage
 
     // Instruction Decoder Instantiation
 
-    decoder u_decoder (
+    instruction_decoder u_decoder (
         .instr          (if_instr),
         .priv_mode      (csr_priv_mode),
         .mstatus_tsr    (csr_mstatus_tsr),
@@ -164,7 +164,7 @@ module id_stage
     );
 
     // Register File Instantiation
-    regfile u_regfile (
+    gpr_file u_regfile (
         .clk            (clk),
         .rst            (rst),
         
@@ -180,7 +180,7 @@ module id_stage
         .rd_wdata       (wb_rd_wdata)
     );
 
-    fp_regfile u_fp_regfile (
+    fpr_file u_fp_regfile (
         .clk            (clk),
         .rst            (rst),
         .fs1_addr       (rs1_addr),
diff --git a/rv64cpu/rtl/core/privileged/trap_controller.sv b/rv64cpu/rtl/core/privileged/trap_controller.sv
index 0969fdc..246b392 100644
--- a/rv64cpu/rtl/core/privileged/trap_controller.sv
+++ b/rv64cpu/rtl/core/privileged/trap_controller.sv
@@ -18,7 +18,7 @@
 // Description: Privileged-level Trap Controller (Exception and Interrupt Handling)
 //              Detects exceptions/interrupts, triggers context saving, and generates global pipeline flush and PC jump signals
 
-module trap_ctrl 
+module trap_controller
     import rv64_pkg::*;
     import csr_pkg::*;
 (
diff --git a/rv64cpu/rtl/core/registers/fpr_file.sv b/rv64cpu/rtl/core/registers/fpr_file.sv
index 67e83f9..7522b5f 100644
--- a/rv64cpu/rtl/core/registers/fpr_file.sv
+++ b/rv64cpu/rtl/core/registers/fpr_file.sv
@@ -4,7 +4,7 @@
 // File path: rtl/core/fp_regfile.sv
 // Description: 32-entry 64-bit floating-point register file for RV64F/RV64D.
 
-module fp_regfile
+module fpr_file
     import rv64_pkg::*;
 (
     input  logic            clk,
diff --git a/rv64cpu/rtl/core/registers/gpr_file.sv b/rv64cpu/rtl/core/registers/gpr_file.sv
index dbc3c04..4ddf200 100644
--- a/rv64cpu/rtl/core/registers/gpr_file.sv
+++ b/rv64cpu/rtl/core/registers/gpr_file.sv
@@ -17,7 +17,7 @@
 // File path: rtl/core/regfile.sv
 // Description: 64-bit Register File
 
-module regfile
+module gpr_file
     import rv64_pkg::*;
 (
     input  logic                      clk,  // Clock signal
diff --git a/rv64cpu/rtl/core/rv64_core.sv b/rv64cpu/rtl/core/rv64_core.sv
index 51c64f8..630fc3d 100644
--- a/rv64cpu/rtl/core/rv64_core.sv
+++ b/rv64cpu/rtl/core/rv64_core.sv
@@ -18,7 +18,7 @@
 // Description: Richard CPU core top-level wrapper (Core Top)
 // Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard Unit
 
-module richard_core
+module rv64_core
     import rv64_pkg::*;
     import csr_pkg::*;
 (
@@ -389,7 +389,7 @@ module richard_core
         end
     end
 
-    mmu_top u_mmu_top (
+    mmu u_mmu_top (
         .clk                  (clk),
         .rst                  (rst),
         .satp_value           (csr_satp_value),
@@ -763,7 +763,7 @@ module richard_core
         .ex_branch_target   (ex_branch_target_out)
     );
 
-    fpu_unit u_fpu_unit (
+    fpu u_fpu_unit (
         .fp_op          (ex_fp_op_in),
         .fp_fmt         (ex_fp_fmt_in),
         .rm             ((ex_fp_rm_in == 3'b111) ? csr_frm_value : ex_fp_rm_in),
@@ -1171,7 +1171,7 @@ module richard_core
         .csr_illegal_access     (csr_illegal_access)
     );
 
-    trap_ctrl u_trap_ctrl (
+    trap_controller u_trap_ctrl (
         .wb_pc               (wb_pc_in),
         .trap_illegal_instr  (trap_illegal_instr),
         .trap_is_ecall       (trap_is_ecall),