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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-08 04:14:34 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-08 04:14:34 +0800 |
| commit | 77884c967d1cbc48afcbaef7e5a35adcb3c5da1b (patch) | |
| tree | 8cc31c1c5115ed909ec9f8751964bfdc96fbd4ad /backend/include/rcc/CodeGen/TargetDescription.h | |
| parent | 10b7e69448f866bcd6893b21d7f78d766252eb11 (diff) | |
| download | rcc-project-77884c967d1cbc48afcbaef7e5a35adcb3c5da1b.tar.gz rcc-project-77884c967d1cbc48afcbaef7e5a35adcb3c5da1b.tar.xz | |
[CodeGen] Implement machine SSA exit
Diffstat (limited to 'backend/include/rcc/CodeGen/TargetDescription.h')
| -rw-r--r-- | backend/include/rcc/CodeGen/TargetDescription.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/backend/include/rcc/CodeGen/TargetDescription.h b/backend/include/rcc/CodeGen/TargetDescription.h index c2a4133..7e41a58 100644 --- a/backend/include/rcc/CodeGen/TargetDescription.h +++ b/backend/include/rcc/CodeGen/TargetDescription.h @@ -72,6 +72,9 @@ public: std::span<const MachineMemOperand *const> MemOperands) const; [[nodiscard]] Expected<void> validateInstruction(const MachineInstr &Instruction, const MachineRegisterInfo &RegInfo) const; + [[nodiscard]] Expected<void> validateTieCompatibility(const MachineOperand &Def, + const MachineOperand &Use, + const MachineRegisterInfo &RegInfo) const; [[nodiscard]] Expected<void> validateCFIInfo(const MachineCFIInfo &Info) const; [[nodiscard]] Expected<void> validateFrameInfo(const MachineFrameInfo &Info) const; [[nodiscard]] Expected<void> validateRegisterInfo(const MachineRegisterInfo &RegInfo) const; @@ -95,10 +98,6 @@ private: const VirtualRegisterInfo &Info) const; [[nodiscard]] std::optional<RegisterClassID> effectiveRegisterClass(const MachineOperand &Operand, const MachineRegisterInfo &RegInfo) const; - [[nodiscard]] Expected<void> validateTieCompatibility(const MachineOperand &Def, - const MachineOperand &Use, - const MachineRegisterInfo &RegInfo) const; - InstructionSet Instructions; TargetRegisterInfo Registers; TargetMIRTextInfo MIRText; |
