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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-03 19:24:30 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-03 19:24:30 +0800
commit432efe39315ed5ad0162f9c08dbf10941bc21dc1 (patch)
tree46622290cabfaeb8f4db1729aca6f0725739e08c /backend/lib/CodeGen/MachineRegisterInfo.cpp
parent6580ac1c05bd1cbccd2dcd71fd9c2a384ae3db56 (diff)
downloadrcc-project-432efe39315ed5ad0162f9c08dbf10941bc21dc1.tar.gz
rcc-project-432efe39315ed5ad0162f9c08dbf10941bc21dc1.tar.xz
[CodeGen] Add target MIR text schema
Diffstat (limited to 'backend/lib/CodeGen/MachineRegisterInfo.cpp')
-rw-r--r--backend/lib/CodeGen/MachineRegisterInfo.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/backend/lib/CodeGen/MachineRegisterInfo.cpp b/backend/lib/CodeGen/MachineRegisterInfo.cpp
index c31b38b..3784b22 100644
--- a/backend/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/backend/lib/CodeGen/MachineRegisterInfo.cpp
@@ -94,6 +94,7 @@ Expected<void> MachineRegisterInfo::eraseVirtualRegister(Register Reg) {
Info->get().Bank.reset();
Info->get().RegClass.reset();
Info->get().AllocationHints.clear();
+ Info->get().TargetFlags = 0;
return {};
}
@@ -188,6 +189,18 @@ Expected<void> MachineRegisterInfo::addAllocationHint(Register Reg, PhysicalRegi
return {};
}
+Expected<void> MachineRegisterInfo::setTargetRegisterFlags(Register Reg, std::uint8_t Flags) {
+ auto Info = virtualRegisterInfo(Reg);
+ if (!Info)
+ return std::unexpected(Info.error());
+ Info->get().TargetFlags = Flags;
+ return {};
+}
+
+Expected<void> MachineRegisterInfo::clearTargetRegisterFlags(Register Reg) {
+ return setTargetRegisterFlags(Reg, 0);
+}
+
void MachineRegisterInfo::clearAllVirtualRegisterTypes() noexcept {
for (VirtualRegisterInfo &Info : VirtualRegisters) {
if (!Info.IsTombstone)