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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-24 17:30:29 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-24 17:30:29 +0800
commit81afb6570000472c182e5b1f540f69382602aaad (patch)
tree4fdab5a642e5088cd456662d438e96d195fdc3d4 /backend/lib/Target/RISCV/RISCV.h
parent47d0d5140b4616ae4dd7c6d2c3c089ccbfc3b009 (diff)
downloadrcc-project-81afb6570000472c182e5b1f540f69382602aaad.tar.gz
rcc-project-81afb6570000472c182e5b1f540f69382602aaad.tar.xz
[RISCV] Match LLVM emergency spill layout
Diffstat (limited to 'backend/lib/Target/RISCV/RISCV.h')
-rw-r--r--backend/lib/Target/RISCV/RISCV.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/backend/lib/Target/RISCV/RISCV.h b/backend/lib/Target/RISCV/RISCV.h
index a2212d4..0a4038b 100644
--- a/backend/lib/Target/RISCV/RISCV.h
+++ b/backend/lib/Target/RISCV/RISCV.h
@@ -37,8 +37,8 @@ createSchedulingModel(const TargetSchedulingHooks &Hooks);
[[nodiscard]] const TargetMemoryFoldingInfo &memoryFoldingInfo() noexcept;
[[nodiscard]] const TargetPseudoExpansionInfo &pseudoExpansionInfo() noexcept;
[[nodiscard]] MachineOptimizationPipelineTargetInfo
-optimizationPipelineInfo(const RISCVSubtarget &Subtarget,
- bool EmitSchedulerDebugOutput = false) noexcept;
+optimizationPipelineInfo(const RISCVSubtarget &Subtarget, bool EmitSchedulerDebugOutput = false,
+ bool EmitFrameDebugOutput = false) noexcept;
} // namespace riscv
} // namespace rcc