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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-22 18:49:08 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-22 18:49:08 +0800 |
| commit | 8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7 (patch) | |
| tree | 51278f18d8954e7abb5820cb9d529e3d5e5f322b /backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc | |
| parent | 9ca9fb23124e8c5d714e9668210855a23dd2a72f (diff) | |
| download | rcc-project-8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7.tar.gz rcc-project-8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7.tar.xz | |
[CodeGen] Generate RISC-V macro fusion rules
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc index 7bb30e5..13ea700 100644 --- a/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc +++ b/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc @@ -188,7 +188,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 @@ -233,7 +233,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 @@ -248,7 +248,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 @@ -263,7 +263,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 @@ -666,7 +666,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 |