diff options
| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-22 19:16:18 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-22 19:16:18 +0800 |
| commit | 75f1223070749b0df3002226ebbb474c68c71f90 (patch) | |
| tree | e3b386180f6ea394381862d5ff9b5394ac0a6481 /backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc | |
| parent | 36b0be1ec1558f88d4f031a1817c3a4c2cba07a6 (diff) | |
| download | rcc-project-75f1223070749b0df3002226ebbb474c68c71f90.tar.gz rcc-project-75f1223070749b0df3002226ebbb474c68c71f90.tar.xz | |
[RISCV] Generate MC pseudo lowering
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc b/backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc new file mode 100644 index 0000000..a505281 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc @@ -0,0 +1,35 @@ +mc_pseudo_expansions: + - + pseudo: PseudoBR + opcode: JAL + operands: + - { register: X0 } + - { operand: 0 } + - + pseudo: PseudoBRIND + opcode: JALR + operands: + - { register: X0 } + - { operand: 0 } + - { operand: 1 } + - + pseudo: PseudoRET + opcode: JALR + operands: + - { register: X0 } + - { register: X1 } + - { immediate: 0 } + - + pseudo: ReadFFLAGS + opcode: CSRRS + operands: + - { operand: 0 } + - { immediate: 1 } + - { register: X0 } + - + pseudo: WriteFFLAGS + opcode: CSRRW + operands: + - { register: X0 } + - { immediate: 1 } + - { operand: 0 } |