[RISCV] Match LLVM emergency spill layout

1 files changed, 4 insertions, 2 deletions

diff --git a/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp b/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
index cfc5583..45c557a 100644
--- a/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
+++ b/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
@@ -5,8 +5,9 @@
 
 namespace rcc::riscv {
 
-MachineOptimizationPipelineTargetInfo
-optimizationPipelineInfo(const RISCVSubtarget &Subtarget, bool EmitSchedulerDebugOutput) noexcept {
+MachineOptimizationPipelineTargetInfo optimizationPipelineInfo(const RISCVSubtarget &Subtarget,
+                                                               bool EmitSchedulerDebugOutput,
+                                                               bool EmitFrameDebugOutput) noexcept {
   return {
       .InstrInfo = instrInfo(),
       .Combiner = machineCombinerInfo(),
@@ -15,6 +16,7 @@ optimizationPipelineInfo(const RISCVSubtarget &Subtarget, bool EmitSchedulerDebu
       .PseudoExpansion = pseudoExpansionInfo(),
       .SchedulingModel = Subtarget.schedulingModel(),
       .SchedulerOptions = {.EmitDebugOutput = EmitSchedulerDebugOutput},
+      .FrameOptions = {.EmitDebugOutput = EmitFrameDebugOutput},
   };
 }