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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-19 02:50:30 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-19 02:50:30 +0800 |
| commit | 6c97d54954112be9a5badacaec8efa1d05bd7d15 (patch) | |
| tree | 9eb4d5db7f05218759e6f6d49cf90ca65f1e53f8 /backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp | |
| parent | f5c592905e6e1ef4b78337d76c8215e543607b8d (diff) | |
| download | rcc-project-6c97d54954112be9a5badacaec8efa1d05bd7d15.tar.gz rcc-project-6c97d54954112be9a5badacaec8efa1d05bd7d15.tar.xz | |
[RISCV][GlobalISel] Generate indirect branch selection
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp index e24c199..99c261c 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp +++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp @@ -36,7 +36,8 @@ struct SpillForm final { if (Class == registerClassID(RegisterClass::GPR) || Class == registerClassID(RegisterClass::GPRC) || Class == registerClassID(RegisterClass::GPR_NX0) || - Class == registerClassID(RegisterClass::GPR_NX0_NX2)) { + Class == registerClassID(RegisterClass::GPR_NX0_NX2) || + Class == registerClassID(RegisterClass::GPRJALRNonX7)) { return SpillForm{InstructionOpcode::LD, InstructionOpcode::SD, 8}; } if (Class == registerClassID(RegisterClass::FPR64) || |