aboutsummaryrefslogtreecommitdiff
path: root/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp')
-rw-r--r--backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
index e24c199..99c261c 100644
--- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
+++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
@@ -36,7 +36,8 @@ struct SpillForm final {
if (Class == registerClassID(RegisterClass::GPR) ||
Class == registerClassID(RegisterClass::GPRC) ||
Class == registerClassID(RegisterClass::GPR_NX0) ||
- Class == registerClassID(RegisterClass::GPR_NX0_NX2)) {
+ Class == registerClassID(RegisterClass::GPR_NX0_NX2) ||
+ Class == registerClassID(RegisterClass::GPRJALRNonX7)) {
return SpillForm{InstructionOpcode::LD, InstructionOpcode::SD, 8};
}
if (Class == registerClassID(RegisterClass::FPR64) ||