[RISCV] Make target memory operands optional

1 files changed, 3 insertions, 1 deletions

diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
index 055b67b..d14e802 100644
--- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
+++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
@@ -178,9 +178,11 @@ public:
     for (const InstructionOpcode OpcodeValue : {Form->Load, Form->Store}) {
       const InstructionDescriptor *Instruction =
           Target.instructionDescriptor(targetOpcode(OpcodeValue));
+      const InstructionFlag MemoryFlag =
+          OpcodeValue == Form->Load ? InstructionFlag::MayLoad : InstructionFlag::MayStore;
       if (Instruction == nullptr || Instruction->Operands.size() != 3 ||
           !Instruction->Operands[1].Kinds.contains(MachineOperand::Kind::FrameIndex) ||
-          !Instruction->RequiresMemoryOperands) {
+          !Instruction->Flags.has(MemoryFlag)) {
         return makeUnexpected(ErrorCode::InternalError,
                               "RV64GC spill instruction descriptor is incomplete");
       }