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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-11 23:44:57 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-11 23:44:57 +0800 |
| commit | e6cd1347cc2c76babe56842e1b7bd05d68fe9584 (patch) | |
| tree | d00769b50841cbcea907b76ac006b366147325dc /backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp | |
| parent | 234d7d3bec020103e46daaff39d207d978479730 (diff) | |
| download | rcc-project-e6cd1347cc2c76babe56842e1b7bd05d68fe9584.tar.gz rcc-project-e6cd1347cc2c76babe56842e1b7bd05d68fe9584.tar.xz | |
[RISCV] Model typed floating-point register views
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp index aee09a9..055b67b 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp +++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp @@ -81,10 +81,14 @@ createStackMemoryOperand(MachineIRBuilder &Builder, FrameIndex StackSlot, Memory PhysicalRegisterID::X25, PhysicalRegisterID::X26, PhysicalRegisterID::X27, }; const std::array FPRs{ - PhysicalRegisterID::F8, PhysicalRegisterID::F9, PhysicalRegisterID::F18, - PhysicalRegisterID::F19, PhysicalRegisterID::F20, PhysicalRegisterID::F21, - PhysicalRegisterID::F22, PhysicalRegisterID::F23, PhysicalRegisterID::F24, - PhysicalRegisterID::F25, PhysicalRegisterID::F26, PhysicalRegisterID::F27, + PhysicalRegisterID::F8_D, PhysicalRegisterID::F9_D, PhysicalRegisterID::F18_D, + PhysicalRegisterID::F19_D, PhysicalRegisterID::F20_D, PhysicalRegisterID::F21_D, + PhysicalRegisterID::F22_D, PhysicalRegisterID::F23_D, PhysicalRegisterID::F24_D, + PhysicalRegisterID::F25_D, PhysicalRegisterID::F26_D, PhysicalRegisterID::F27_D, + PhysicalRegisterID::F8_F, PhysicalRegisterID::F9_F, PhysicalRegisterID::F18_F, + PhysicalRegisterID::F19_F, PhysicalRegisterID::F20_F, PhysicalRegisterID::F21_F, + PhysicalRegisterID::F22_F, PhysicalRegisterID::F23_F, PhysicalRegisterID::F24_F, + PhysicalRegisterID::F25_F, PhysicalRegisterID::F26_F, PhysicalRegisterID::F27_F, }; const auto Matches = [Number](PhysicalRegisterID ID) { return Number == static_cast<std::uint32_t>(ID); @@ -96,9 +100,12 @@ createStackMemoryOperand(MachineIRBuilder &Builder, FrameIndex StackSlot, Memory const std::uint32_t Number = Reg.number(); const std::uint32_t X8 = static_cast<std::uint32_t>(PhysicalRegisterID::X8); const std::uint32_t X15 = static_cast<std::uint32_t>(PhysicalRegisterID::X15); - const std::uint32_t F8 = static_cast<std::uint32_t>(PhysicalRegisterID::F8); - const std::uint32_t F15 = static_cast<std::uint32_t>(PhysicalRegisterID::F15); - return (Number >= X8 && Number <= X15) || (Number >= F8 && Number <= F15); + const std::uint32_t F8D = static_cast<std::uint32_t>(PhysicalRegisterID::F8_D); + const std::uint32_t F15D = static_cast<std::uint32_t>(PhysicalRegisterID::F15_D); + const std::uint32_t F8F = static_cast<std::uint32_t>(PhysicalRegisterID::F8_F); + const std::uint32_t F15F = static_cast<std::uint32_t>(PhysicalRegisterID::F15_F); + return (Number >= X8 && Number <= X15) || (Number >= F8D && Number <= F15D) || + (Number >= F8F && Number <= F15F); } class RISCVRegisterAllocationInfo final : public TargetRegisterAllocationInfo { |