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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-25 01:43:04 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-25 01:43:04 +0800 |
| commit | 9e89d1d718977749ca798b27b7ad45e1781602c2 (patch) | |
| tree | e4ab1a06bb0f742792474153071bad94ff279f06 /backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc | |
| parent | b8fb9248e77e492c630ca135d1bfd58b74f9752a (diff) | |
| download | rcc-project-9e89d1d718977749ca798b27b7ad45e1781602c2.tar.gz rcc-project-9e89d1d718977749ca798b27b7ad45e1781602c2.tar.xz | |
[RISCV] Implement Zcmp move merging
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc index 9e5a237..4806ec4 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc +++ b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc @@ -378,6 +378,18 @@ register_classes: lanes: 1 registers: [X6, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] allocation_order: [X10, X11, X12, X13, X14, X15, X16, X17, X6, X28, X29, X30, X31, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27] + - + id: 13 + symbol: SR07 + name: SR07 + bank: GPR + superclasses: [GPR] + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [X8, X9, X18, X19, X20, X21, X22, X23] + allocation_order: [X8, X9, X18, X19, X20, X21, X22, X23] register_masks: - |