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authorRichard-Qin-X <richard.qin.001@gmail.com>2026-08-25 03:11:23 +0800
committerRichard-Qin-X <richard.qin.001@gmail.com>2026-08-25 03:11:23 +0800
commitf5d9ddc085055d28d6f9fb3730c3566097f43fb2 (patch)
treed1ca89a409a0d1a167e79e3d1693c22bcfd823a9 /backend/lib/Target
parentc3932f55208e3fe2019d26a0e5af421c0b644872 (diff)
downloadrcc-project-f5d9ddc085055d28d6f9fb3730c3566097f43fb2.tar.gz
rcc-project-f5d9ddc085055d28d6f9fb3730c3566097f43fb2.tar.xz
[CodeGen] Implement the greedy register allocator pipeline
Diffstat (limited to 'backend/lib/Target')
-rw-r--r--backend/lib/Target/RISCV/RISCVPipeline.cpp10
-rw-r--r--backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp4
2 files changed, 13 insertions, 1 deletions
diff --git a/backend/lib/Target/RISCV/RISCVPipeline.cpp b/backend/lib/Target/RISCV/RISCVPipeline.cpp
index 854417a..1e18661 100644
--- a/backend/lib/Target/RISCV/RISCVPipeline.cpp
+++ b/backend/lib/Target/RISCV/RISCVPipeline.cpp
@@ -15,9 +15,11 @@
#include "rcc/CodeGen/MachineOptimizationPipeline.h"
#include "rcc/CodeGen/MachinePseudoExpansion.h"
#include "rcc/CodeGen/PHIElimination.h"
+#include "rcc/CodeGen/RegAllocCommon.h"
#include "rcc/CodeGen/RegAllocPBQP.h"
#include "rcc/CodeGen/TargetDescription.h"
#include "rcc/CodeGen/TwoAddressInstructionPass.h"
+#include "rcc/CodeGen/VirtRegMap.h"
#include <memory>
#include <ranges>
@@ -86,7 +88,10 @@ template <typename PassT, typename... ArgumentT>
Options.DebugPrologueEpilogue));
if (!Added)
return std::unexpected(Added.error());
- return addPass<PBQPAllocatorPass>(Pipeline, registerAllocationInfo());
+ Added = addPass<PBQPAllocatorPass>(Pipeline, registerAllocationInfo());
+ if (!Added)
+ return std::unexpected(Added.error());
+ return addPass<VirtualRegisterRewritePass>(Pipeline);
}
[[nodiscard]] Expected<void> addCompleteRegistry(MachineFunctionPassManager &Pipeline,
@@ -98,6 +103,9 @@ template <typename PassT, typename... ArgumentT>
Added = addSSAExitPipeline(Pipeline, Subtarget, Options);
if (!Added)
return std::unexpected(Added.error());
+ Added = Pipeline.addPass(createGreedyAllocatorPass(registerAllocationInfo()));
+ if (!Added)
+ return std::unexpected(Added.error());
Added = addRegisterAllocationPipeline(Pipeline, Subtarget, Options);
if (!Added)
return std::unexpected(Added.error());
diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
index 99c261c..2b34f53 100644
--- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
+++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
@@ -60,10 +60,14 @@ createStackMemoryOperand(MachineIRBuilder &Builder, FrameIndex StackSlot, Memory
auto Align = Alignment::create(AlignmentInBytes);
if (!Align)
return std::unexpected(Align.error());
+ auto Type = LowLevelType::makeCategoryNeutralScalar(SizeInBytes * 8U);
+ if (!Type)
+ return std::unexpected(Type.error());
MachineMemOperandDesc Description;
Description.Accesses = {Access};
Description.Size = *Size;
+ Description.MemoryType = *Type;
Description.Align = *Align;
Description.Base = MemoryBase::frameIndex(StackSlot);
return Builder.function().createMemOperand(std::move(Description));