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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-09 18:31:49 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-09 18:31:49 +0800 |
| commit | 379ff50dcc7ccf977379aee68fa9d10f69065d23 (patch) | |
| tree | e0fac3952d46d0bbcaea32bcfc6087c95fff2992 /backend/unittests/Target/Inputs/RISCVGenericPipeline.mir | |
| parent | 495c675771f43cfa12ab7a426a538be72fec1805 (diff) | |
| download | rcc-project-379ff50dcc7ccf977379aee68fa9d10f69065d23.tar.gz rcc-project-379ff50dcc7ccf977379aee68fa9d10f69065d23.tar.xz | |
[MC] Implement RV64GC assembly emission
Diffstat (limited to 'backend/unittests/Target/Inputs/RISCVGenericPipeline.mir')
| -rw-r--r-- | backend/unittests/Target/Inputs/RISCVGenericPipeline.mir | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir new file mode 100644 index 0000000..d68cd72 --- /dev/null +++ b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir @@ -0,0 +1,12 @@ +--- +name: generic_pipeline +tracksRegLiveness: true +isSSA: true +body: | + bb.0: + liveins: $x1 + %0:gpr(i64) = G_CONSTANT 42 + %1:gpr(i64) = G_CONSTANT 1 + %2:gpr(i64) = G_ADD %0, %1 + $x10 = COPY %2 + PseudoRET implicit $x1, implicit $x10 |