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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-11 17:38:11 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-11 17:38:11 +0800 |
| commit | 4fe5ee649927d54d6fb74904d7b97ad0f63fd587 (patch) | |
| tree | 75f85f5e6cae3a871fe42d025dca04eeb7c31cfd /backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir | |
| parent | 6a7b083f322f4ac47e58cbf9d4d5fd4d1f6fecd0 (diff) | |
| download | rcc-project-4fe5ee649927d54d6fb74904d7b97ad0f63fd587.tar.gz rcc-project-4fe5ee649927d54d6fb74904d7b97ad0f63fd587.tar.xz | |
[RISCV] Legalize fixed-baseline RV64 MachineIR
Diffstat (limited to 'backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir')
| -rw-r--r-- | backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir b/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir index 9695691..1b9ee82 100644 --- a/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir +++ b/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir @@ -5,6 +5,6 @@ isSSA: true body: | bb.0: liveins: $x1 - %0:gpr(i64) = G_CONSTANT 9223372036854775807 + %0:gprb(i64) = G_CONSTANT 9223372036854775807 $x10 = COPY %0 PseudoRET implicit $x1, implicit $x10 |