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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 00:26:10 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-12 00:26:10 +0800 |
| commit | d91d57297bdb30b6363e259ab75d517dc333e292 (patch) | |
| tree | b931c72127e25a4acbf1f7b38ffdcba74ef270c7 /backend/unittests/Target/RISCVTargetTest.cpp | |
| parent | adf3e4f02e330e052dbb75e9601bae5273ccfe6c (diff) | |
| download | rcc-project-d91d57297bdb30b6363e259ab75d517dc333e292.tar.gz rcc-project-d91d57297bdb30b6363e259ab75d517dc333e292.tar.xz | |
[RISCV] Support absolute address operand flags
Diffstat (limited to 'backend/unittests/Target/RISCVTargetTest.cpp')
| -rw-r--r-- | backend/unittests/Target/RISCVTargetTest.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/backend/unittests/Target/RISCVTargetTest.cpp b/backend/unittests/Target/RISCVTargetTest.cpp index 2d1be09..2077496 100644 --- a/backend/unittests/Target/RISCVTargetTest.cpp +++ b/backend/unittests/Target/RISCVTargetTest.cpp @@ -119,9 +119,11 @@ void testABIAndDebugFacts(TestContext &Context) { TextLP64DMask != nullptr && LP64DMask != nullptr && *TextLP64DMask == *LP64DMask, "RV64GC must expose named LP64 and LP64D call-preserved masks"); - Context.expect(MIRText->directOperandFlagMask() == 31 && - MIRText->directOperandFlag("riscv-call") == 1, - "RV64GC MIR target flags must expose the canonical direct-call spelling"); + Context.expect(MIRText->directOperandFlagMask() == 127 && + MIRText->directOperandFlag("riscv-call") == 1 && + MIRText->directOperandFlag("riscv-hi") == 32 && + MIRText->directOperandFlag("riscv-lo") == 64, + "RV64GC MIR target flags must expose canonical call and address spellings"); Context.expect(MIRText->dwarfRegister(X1) == 1, "the return-address register must retain its DWARF register number"); Context.expect(MIRText->dwarfRegister(F31D) == 63 && MIRText->dwarfRegister(F31F) == 63 && |