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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-07 02:15:09 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-07 02:15:09 +0800 |
| commit | e16de95dce32f077361577377d5c52fc4ad78339 (patch) | |
| tree | ea563652a95e6e32eb86ce68845a2005d83a85d5 /backend/unittests/Target/TestTarget.cpp | |
| parent | 76d89700953ddd81cf31ab8f260eddf67e93aa85 (diff) | |
| download | rcc-project-e16de95dce32f077361577377d5c52fc4ad78339.tar.gz rcc-project-e16de95dce32f077361577377d5c52fc4ad78339.tar.xz | |
[RISCV] Add generated RV64GC register description
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
Diffstat (limited to 'backend/unittests/Target/TestTarget.cpp')
| -rw-r--r-- | backend/unittests/Target/TestTarget.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backend/unittests/Target/TestTarget.cpp b/backend/unittests/Target/TestTarget.cpp index 4d31fb9..a367454 100644 --- a/backend/unittests/Target/TestTarget.cpp +++ b/backend/unittests/Target/TestTarget.cpp @@ -25,7 +25,8 @@ namespace { [[nodiscard]] PhysicalRegisterDesc physicalRegister(std::uint32_t Number, const char *Name, std::uint32_t Encoding, std::vector<RegisterUnitLane> Units) { - return PhysicalRegisterDesc{phys(Number), Name, Encoding, std::move(Units)}; + return PhysicalRegisterDesc{phys(Number), Name, Encoding, std::move(Units), + false, false, false, {}}; } [[nodiscard]] RegisterClassDesc |