[CodeGen] Match LLVM branch relaxation semantics

1 files changed, 5 insertions, 0 deletions

diff --git a/backend/utils/TableGen/Common/CodeGenInstruction.cpp b/backend/utils/TableGen/Common/CodeGenInstruction.cpp
index fc6b400..d06fbfc 100644
--- a/backend/utils/TableGen/Common/CodeGenInstruction.cpp
+++ b/backend/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -428,6 +428,7 @@ CodeGenTarget::normalizeImplicitRegisters(const std::vector<SourceImplicitRegist
         .Flags = {},
         .SchedulingClass = HasSchedulingClass ? SchedulingClass->second : 0,
         .EncodingCategory = HasEncodingCategory ? EncodingCategory->second : 0,
+        .SizeInBytes = Instruction.SizeInBytes,
         .AssemblyFormat = HasAssemblyFormat ? AssemblyFormat->second : 0,
         .RequiresMemoryOperands = Instruction.RequiresMemoryOperands,
         .Owner = std::string(*Owner),
@@ -547,6 +548,10 @@ CodeGenTarget::normalizeImplicitRegisters(const std::vector<SourceImplicitRegist
       fail(Instruction.Range, "instruction pseudo flags, owner, and deadline are inconsistent");
       return false;
     }
+    if (Normalized.SizeInBytes != 0 && !HasFlag("ProducesCode")) {
+      fail(Instruction.Range, "only code-producing instructions can declare a byte size");
+      return false;
+    }
     if (Normalized.RequiresMemoryOperands && !HasFlag("MayLoad") && !HasFlag("MayStore")) {
       fail(Instruction.Range, "memory operand requirements need a load or store instruction flag");
       return false;