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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-04-07 21:21:03 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-04-07 21:21:03 +0800 |
| commit | 328d4ef7537a98bab8f6891a0280cda9e03b0cee (patch) | |
| tree | a201ad9d62d2d566feb3da23d578e4df39f9a94a /rv64cpu/CMakeLists.txt | |
| parent | 9c34902e4a763109d7d6251781bcb92f6bc68c56 (diff) | |
| download | rcc-project-328d4ef7537a98bab8f6891a0280cda9e03b0cee.tar.gz rcc-project-328d4ef7537a98bab8f6891a0280cda9e03b0cee.tar.xz | |
feat(tlb): enhance TLB functionality with ASID-targeted flush and additional test cases
Diffstat (limited to 'rv64cpu/CMakeLists.txt')
| -rw-r--r-- | rv64cpu/CMakeLists.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/rv64cpu/CMakeLists.txt b/rv64cpu/CMakeLists.txt index 4649abb..da146d5 100644 --- a/rv64cpu/CMakeLists.txt +++ b/rv64cpu/CMakeLists.txt @@ -1,4 +1,9 @@ cmake_minimum_required(VERSION 3.20) + +if(POLICY CMP0144) + cmake_policy(SET CMP0144 NEW) +endif() + project(richard_cpu VERSION 0.1.0 DESCRIPTION "RV64IMAZicsr_Zifencei Five-Stage Pipelined CPU SoC" @@ -54,6 +59,7 @@ file(MAKE_DIRECTORY ${CMAKE_SOURCE_DIR}/waves) # ─── Testing ──────────────────────────────────────────────────────────────────── enable_testing() +include(CTest) # ─── Testbench Subdirectory ───────────────────────────────────────────────────── add_subdirectory(tb) |