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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-04-07 22:42:49 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-04-07 22:42:49 +0800 |
| commit | 639212a826659c591db3202607c4a47e1049b92a (patch) | |
| tree | 74ebfcef8d5cd589fcdfc11ffba8f588f3fd50f9 /rv64cpu/README.md | |
| parent | 328d4ef7537a98bab8f6891a0280cda9e03b0cee (diff) | |
| download | rcc-project-639212a826659c591db3202607c4a47e1049b92a.tar.gz rcc-project-639212a826659c591db3202607c4a47e1049b92a.tar.xz | |
refactor: standardize interrupt signal naming across the codebase
Diffstat (limited to 'rv64cpu/README.md')
| -rw-r--r-- | rv64cpu/README.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rv64cpu/README.md b/rv64cpu/README.md index 72b3546..a7e62a5 100644 --- a/rv64cpu/README.md +++ b/rv64cpu/README.md @@ -130,7 +130,7 @@ richard-cpu/ |---|---| | P1 | RV64I five-stage pipeline + hazard handling (Done) | | P2 | CSR + M/S/U privilege levels + Trap (Done) | -| P3 | MMU (Sv39 TLB + PTW) | +| P3 | MMU (TLB + PTW) | | P4 | Cache + AXI4-Full Burst | | P5 | Peripherals + AXI4-Lite bridge + SoC integration | | P6 | Pass riscv-arch-test (In Progress: strict suites above all pass) | |