refactor: align RTL module names with files

2 files changed, 2 insertions, 2 deletions

diff --git a/rv64cpu/rtl/core/execute/instruction_decoder.sv b/rv64cpu/rtl/core/execute/instruction_decoder.sv
index c39a637..14d9559 100644
--- a/rv64cpu/rtl/core/execute/instruction_decoder.sv
+++ b/rv64cpu/rtl/core/execute/instruction_decoder.sv
@@ -19,7 +19,7 @@
 //              Translates 32-bit instructions into control signals for the pipeline.
 //              C is handled by the IF-stage decompressor before this decoder.
 
-module decoder
+module instruction_decoder
     import rv64_pkg::*;
 (
     input  logic [31:0]       instr,          // 32-bit instruction
diff --git a/rv64cpu/rtl/core/execute/integer_alu.sv b/rv64cpu/rtl/core/execute/integer_alu.sv
index 08635ce..833f902 100644
--- a/rv64cpu/rtl/core/execute/integer_alu.sv
+++ b/rv64cpu/rtl/core/execute/integer_alu.sv
@@ -17,7 +17,7 @@
 // File path: rtl/core/alu.sv
 // Description: 64-bit Arithmetic Logic Unit (ALU)
 
-module alu
+module integer_alu
     import rv64_pkg::*;
 (
     input  alu_op_t          alu_op,     // ALU operation select (from decoder)