refactor: align RTL module names with files

2 files changed, 4 insertions, 4 deletions

diff --git a/rv64cpu/rtl/core/pipeline/ex_stage.sv b/rv64cpu/rtl/core/pipeline/ex_stage.sv
index 287bfd7..2758ffc 100644
--- a/rv64cpu/rtl/core/pipeline/ex_stage.sv
+++ b/rv64cpu/rtl/core/pipeline/ex_stage.sv
@@ -88,7 +88,7 @@ module ex_stage
 
     // --------------
     // Instantiate the core computing engine ALU
-    alu alu_inst (
+    integer_alu alu_inst (
         .alu_op         (ex_alu_op),
         .operand_a      (alu_operand_a),
         .operand_b      (alu_operand_b),
diff --git a/rv64cpu/rtl/core/pipeline/id_stage.sv b/rv64cpu/rtl/core/pipeline/id_stage.sv
index 9003b42..1cf447a 100644
--- a/rv64cpu/rtl/core/pipeline/id_stage.sv
+++ b/rv64cpu/rtl/core/pipeline/id_stage.sv
@@ -108,7 +108,7 @@ module id_stage
 
     // Instruction Decoder Instantiation
 
-    decoder u_decoder (
+    instruction_decoder u_decoder (
         .instr          (if_instr),
         .priv_mode      (csr_priv_mode),
         .mstatus_tsr    (csr_mstatus_tsr),
@@ -164,7 +164,7 @@ module id_stage
     );
 
     // Register File Instantiation
-    regfile u_regfile (
+    gpr_file u_regfile (
         .clk            (clk),
         .rst            (rst),
         
@@ -180,7 +180,7 @@ module id_stage
         .rd_wdata       (wb_rd_wdata)
     );
 
-    fp_regfile u_fp_regfile (
+    fpr_file u_fp_regfile (
         .clk            (clk),
         .rst            (rst),
         .fs1_addr       (rs1_addr),