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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 03:16:17 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-11-07 03:16:17 +0800 |
| commit | e0948e3fc10029ba4bb4d48d7b5daae94fe575b9 (patch) | |
| tree | 99c5427ff631b03fcad311288604e7dd02ee3557 /rv64cpu/rtl/core/rv64_core.sv | |
| parent | 6f57dd79572c177b775a934bee54ceb85a55c28a (diff) | |
| download | rcc-project-e0948e3fc10029ba4bb4d48d7b5daae94fe575b9.tar.gz rcc-project-e0948e3fc10029ba4bb4d48d7b5daae94fe575b9.tar.xz | |
refactor: align RTL module names with files
Diffstat (limited to 'rv64cpu/rtl/core/rv64_core.sv')
| -rw-r--r-- | rv64cpu/rtl/core/rv64_core.sv | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/rv64cpu/rtl/core/rv64_core.sv b/rv64cpu/rtl/core/rv64_core.sv index 51c64f8..630fc3d 100644 --- a/rv64cpu/rtl/core/rv64_core.sv +++ b/rv64cpu/rtl/core/rv64_core.sv @@ -18,7 +18,7 @@ // Description: Richard CPU core top-level wrapper (Core Top) // Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard Unit -module richard_core +module rv64_core import rv64_pkg::*; import csr_pkg::*; ( @@ -389,7 +389,7 @@ module richard_core end end - mmu_top u_mmu_top ( + mmu u_mmu_top ( .clk (clk), .rst (rst), .satp_value (csr_satp_value), @@ -763,7 +763,7 @@ module richard_core .ex_branch_target (ex_branch_target_out) ); - fpu_unit u_fpu_unit ( + fpu u_fpu_unit ( .fp_op (ex_fp_op_in), .fp_fmt (ex_fp_fmt_in), .rm ((ex_fp_rm_in == 3'b111) ? csr_frm_value : ex_fp_rm_in), @@ -1171,7 +1171,7 @@ module richard_core .csr_illegal_access (csr_illegal_access) ); - trap_ctrl u_trap_ctrl ( + trap_controller u_trap_ctrl ( .wb_pc (wb_pc_in), .trap_illegal_instr (trap_illegal_instr), .trap_is_ecall (trap_is_ecall), |