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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-03-18 03:09:38 +0800 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-03-18 03:09:38 +0800 |
| commit | 48489af495086d794f1b57bbb62ea1d8aca86ac5 (patch) | |
| tree | 7ca1900f20416a20f13b4a8cf03661c8995d2786 /rv64cpu/tb/CMakeLists.txt | |
| parent | 2e6e4c0caa855131602f5a816968b90908baa2df (diff) | |
| download | rcc-project-48489af495086d794f1b57bbb62ea1d8aca86ac5.tar.gz rcc-project-48489af495086d794f1b57bbb62ea1d8aca86ac5.tar.xz | |
CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard Unit
Diffstat (limited to 'rv64cpu/tb/CMakeLists.txt')
| -rw-r--r-- | rv64cpu/tb/CMakeLists.txt | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt index 11fb3fc..1b6173a 100644 --- a/rv64cpu/tb/CMakeLists.txt +++ b/rv64cpu/tb/CMakeLists.txt @@ -173,14 +173,30 @@ add_verilator_target( # ═══════════════════════════════════════════════════════════════════════════════════ # Core Integration Test # ═══════════════════════════════════════════════════════════════════════════════════ -# -# add_verilator_target( -# NAME tb_core -# TOP_MODULE richard_core -# SOURCES ${ALL_RTL_SOURCES} -# INCLUDE_DIRS ${RTL_COMMON_INCLUDES} -# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/core/tb_core.cc -# ) + +add_verilator_target( + NAME tb_core + TOP_MODULE richard_core + SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv + ${RTL_CORE_DIR}/alu.sv + ${RTL_CORE_DIR}/branch_unit.sv + ${RTL_CORE_DIR}/decoder.sv + ${RTL_CORE_DIR}/regfile.sv + ${RTL_CORE_DIR}/if_stage.sv + ${RTL_CORE_DIR}/if_id_reg.sv + ${RTL_CORE_DIR}/id_stage.sv + ${RTL_CORE_DIR}/id_ex_reg.sv + ${RTL_CORE_DIR}/ex_stage.sv + ${RTL_CORE_DIR}/ex_mem_reg.sv + ${RTL_CORE_DIR}/mem_stage.sv + ${RTL_CORE_DIR}/mem_wb_reg.sv + ${RTL_CORE_DIR}/wb_stage.sv + ${RTL_CORE_DIR}/hazard_unit.sv + ${RTL_CORE_DIR}/richard_core.sv + INCLUDE_DIRS ${RTL_COMMON_INCLUDES} + TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/core/tb_core.cc + EXTRA_FLAGS -Wno-PINCONNECTEMPTY +) # ═══════════════════════════════════════════════════════════════════════════════════ # SoC Integration Test |