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| author | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 16:51:29 +0000 |
|---|---|---|
| committer | Richard Qin <richard.qin.x@gmail.com> | 2026-03-17 16:51:29 +0000 |
| commit | abddef6c366a4a8e8f878158cf1bac14f9ad59b2 (patch) | |
| tree | 61c0bef5b807090d4fc619ae1f744b034ff4b866 /rv64cpu/tb/CMakeLists.txt | |
| parent | cd638dacbe7d0f890206209317cc119246cf700b (diff) | |
| download | rcc-project-abddef6c366a4a8e8f878158cf1bac14f9ad59b2.tar.gz rcc-project-abddef6c366a4a8e8f878158cf1bac14f9ad59b2.tar.xz | |
docs: Finalized Richard CPU RTL architectural and naming convention audit report.
No source code changes were made; this branch serves as the finalized state for the provided audit.
Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
Diffstat (limited to 'rv64cpu/tb/CMakeLists.txt')
| -rw-r--r-- | rv64cpu/tb/CMakeLists.txt | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt index cd419f9..7ca5bf0 100644 --- a/rv64cpu/tb/CMakeLists.txt +++ b/rv64cpu/tb/CMakeLists.txt @@ -114,6 +114,33 @@ add_verilator_target( INCLUDE_DIRS ${RTL_COMMON_INCLUDES} TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_ex_stage.cc ) + +add_verilator_target( + NAME tb_ex_mem_reg + TOP_MODULE ex_mem_reg + SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv + ${RTL_CORE_DIR}/ex_mem_reg.sv + INCLUDE_DIRS ${RTL_COMMON_INCLUDES} + TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_ex_mem_reg.cc +) + +add_verilator_target( + NAME tb_mem_stage + TOP_MODULE mem_stage + SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv + ${RTL_CORE_DIR}/mem_stage.sv + INCLUDE_DIRS ${RTL_COMMON_INCLUDES} + TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_mem_stage.cc +) + +add_verilator_target( + NAME tb_mem_wb_reg + TOP_MODULE mem_wb_reg + SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv + ${RTL_CORE_DIR}/mem_wb_reg.sv + INCLUDE_DIRS ${RTL_COMMON_INCLUDES} + TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_mem_wb_reg.cc +) # # add_verilator_target( # NAME tb_csr |