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-rw-r--r--backend/include/rcc/CodeGen/TargetCodeGen.h34
1 files changed, 34 insertions, 0 deletions
diff --git a/backend/include/rcc/CodeGen/TargetCodeGen.h b/backend/include/rcc/CodeGen/TargetCodeGen.h
index b1be1f6..f2aac5d 100644
--- a/backend/include/rcc/CodeGen/TargetCodeGen.h
+++ b/backend/include/rcc/CodeGen/TargetCodeGen.h
@@ -7,12 +7,14 @@
#include "rcc/CodeGen/Register.h"
#include "rcc/Support/Error.h"
+#include <cstddef>
#include <cstdint>
#include <optional>
namespace rcc {
class MachineFunction;
+class MachineBasicBlock;
class MachineInstr;
class MachineRegisterInfo;
class TargetDescription;
@@ -89,6 +91,38 @@ public:
}
};
+class TargetSSAInfo {
+public:
+ virtual ~TargetSSAInfo() = default;
+
+ [[nodiscard]] virtual Expected<bool> isFallthroughEdge(const MachineBasicBlock &From,
+ const MachineBasicBlock &To,
+ const MachineFunction &Function,
+ const TargetDescription &Target) const = 0;
+
+ [[nodiscard]] virtual Expected<bool>
+ rewriteBranchTarget(MachineBasicBlock &Block, MachineBasicBlock &OldTarget,
+ MachineBasicBlock &NewTarget, MachineFunction &Function,
+ const TargetDescription &Target) const = 0;
+
+ [[nodiscard]] virtual Expected<void>
+ insertUnconditionalBranch(MachineBasicBlock &Block, MachineBasicBlock &Target,
+ MachineFunction &Function,
+ const TargetDescription &TargetDescription) const = 0;
+
+ [[nodiscard]] virtual Expected<void> validateCopy(Register Destination,
+ SubRegIndex DestinationSubReg, Register Source,
+ SubRegIndex SourceSubReg,
+ const MachineFunction &Function,
+ const TargetDescription &Target) const = 0;
+
+ [[nodiscard]] virtual Expected<bool> tryConvertToThreeAddress(MachineInstr &, std::size_t,
+ std::size_t, MachineFunction &,
+ const TargetDescription &) const {
+ return false;
+ }
+};
+
} // namespace rcc
#endif // RCC_CODEGEN_TARGETCODEGEN_H