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-rw-r--r--rv64cpu/rtl/core/decoder.sv2
-rw-r--r--rv64cpu/rtl/core/ex_mem_reg.sv195
-rw-r--r--rv64cpu/rtl/core/ex_stage.sv28
-rw-r--r--rv64cpu/rtl/core/id_ex_reg.sv35
-rw-r--r--rv64cpu/rtl/core/id_stage.sv6
-rw-r--r--rv64cpu/rtl/core/mem_stage.sv214
-rw-r--r--rv64cpu/rtl/core/mem_wb_reg.sv132
7 files changed, 595 insertions, 17 deletions
diff --git a/rv64cpu/rtl/core/decoder.sv b/rv64cpu/rtl/core/decoder.sv
index 585a018..c948646 100644
--- a/rv64cpu/rtl/core/decoder.sv
+++ b/rv64cpu/rtl/core/decoder.sv
@@ -80,7 +80,7 @@ module decoder
assign opcode = instr[6:0];
assign rd_addr = instr[11:7];
assign funct3 = instr[14:12];
- assign rs1_addr = instr[19:15];
+ assign rs1_addr = (opcode == OPCODE_LUI) ? 5'b00000 : instr[19:15];
assign rs2_addr = instr[24:20];
assign funct7 = instr[31:25];
diff --git a/rv64cpu/rtl/core/ex_mem_reg.sv b/rv64cpu/rtl/core/ex_mem_reg.sv
new file mode 100644
index 0000000..2cc5e9e
--- /dev/null
+++ b/rv64cpu/rtl/core/ex_mem_reg.sv
@@ -0,0 +1,195 @@
+// Richard CPU
+// Copyright (C) 2026 Richard Qin
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+// File path: rtl/core/ex_mem_reg.sv
+// Description: Execute to Memory Pipeline Register
+// Latches results from the EX stage and bypassed control signals from ID/EX.
+// Supports stall and flush operations.
+
+module ex_mem_reg
+ import rv64_pkg::*;
+(
+ input logic clk,
+ input logic rst,
+
+ // Pipeline Control
+ input logic stall_en,
+ input logic flush_en,
+
+ // ----------------------
+ // Inputs from EX Stage (computed results)
+ input logic [XLEN-1:0] ex_alu_result,
+ input logic ex_branch_taken,
+ input logic [XLEN-1:0] ex_branch_target,
+
+ // ----------------------
+ // Bypassed Inputs from ID/EX Register
+
+ // Data/Operands
+ input logic [XLEN-1:0] ex_rs1_rdata, // Needed for CSRRW/RS/RC
+ input logic [XLEN-1:0] ex_rs2_rdata, // Needed for store data
+ input logic [4:0] ex_rs1_addr, // Serves as zimm for CSRRWI/SI/CI
+ input logic [XLEN-1:0] ex_pc, // PC passed along for exceptions/CSRs
+ input logic [XLEN-1:0] ex_imm, // Imm passed for CSR writes
+
+ // Memory Control
+ input logic ex_is_load,
+ input logic ex_is_store,
+ input logic [2:0] ex_mem_size,
+
+ // Writeback Control
+ input logic ex_reg_write_en,
+ input logic [4:0] ex_rd_addr,
+ input logic [1:0] ex_wb_sel,
+
+ // System / Exception Control
+ input logic ex_is_csr,
+ input logic [2:0] ex_csr_op,
+ input logic ex_illegal_instr,
+ input logic ex_is_ecall,
+ input logic ex_is_ebreak,
+ input logic ex_is_mret,
+ input logic ex_is_sret,
+ input logic ex_is_wfi,
+ input logic ex_is_sfence_vma,
+ input logic ex_is_fence,
+ input logic ex_is_fence_i,
+
+
+ // ----------------------
+ // Outputs to MEM Stage
+
+ // Data/Operands
+ output logic [XLEN-1:0] mem_alu_result,
+ output logic mem_branch_taken,
+ output logic [XLEN-1:0] mem_branch_target,
+ output logic [XLEN-1:0] mem_rs1_rdata,
+ output logic [XLEN-1:0] mem_rs2_rdata,
+ output logic [4:0] mem_rs1_addr,
+ output logic [XLEN-1:0] mem_pc,
+ output logic [XLEN-1:0] mem_imm,
+
+ // Memory Control
+ output logic mem_is_load,
+ output logic mem_is_store,
+ output logic [2:0] mem_mem_size,
+
+ // Writeback Control
+ output logic mem_reg_write_en,
+ output logic [4:0] mem_rd_addr,
+ output logic [1:0] mem_wb_sel,
+
+ // System / Exception Control
+ output logic mem_is_csr,
+ output logic [2:0] mem_csr_op,
+ output logic mem_illegal_instr,
+ output logic mem_is_ecall,
+ output logic mem_is_ebreak,
+ output logic mem_is_mret,
+ output logic mem_is_sret,
+ output logic mem_is_wfi,
+ output logic mem_is_sfence_vma,
+ output logic mem_is_fence,
+ output logic mem_is_fence_i
+);
+
+ always_ff @(posedge clk) begin
+ if (rst) begin
+ mem_alu_result <= '0;
+ mem_branch_taken <= '0;
+ mem_branch_target <= '0;
+ mem_rs1_rdata <= '0;
+ mem_rs2_rdata <= '0;
+ mem_rs1_addr <= '0;
+ mem_pc <= '0;
+ mem_imm <= '0;
+
+ // Critical control signals must be zeroed out
+ mem_is_load <= '0;
+ mem_is_store <= '0;
+ mem_mem_size <= '0;
+ mem_reg_write_en <= '0;
+ mem_rd_addr <= '0;
+ mem_wb_sel <= '0;
+
+ // Exceptions and system control
+ mem_is_csr <= '0;
+ mem_csr_op <= '0;
+ mem_illegal_instr <= '0;
+ mem_is_ecall <= '0;
+ mem_is_ebreak <= '0;
+ mem_is_mret <= '0;
+ mem_is_sret <= '0;
+ mem_is_wfi <= '0;
+ mem_is_sfence_vma <= '0;
+ mem_is_fence <= '0;
+ mem_is_fence_i <= '0;
+
+ end else if (flush_en) begin
+ // Critical control signals must be zeroed out
+ mem_branch_taken <= '0;
+ mem_is_load <= '0;
+ mem_is_store <= '0;
+ mem_mem_size <= '0;
+ mem_reg_write_en <= '0;
+ mem_rd_addr <= '0;
+ mem_wb_sel <= '0;
+
+ // Exceptions and system control
+ mem_is_csr <= '0;
+ mem_csr_op <= '0;
+ mem_illegal_instr <= '0;
+ mem_is_ecall <= '0;
+ mem_is_ebreak <= '0;
+ mem_is_mret <= '0;
+ mem_is_sret <= '0;
+ mem_is_wfi <= '0;
+ mem_is_sfence_vma <= '0;
+ mem_is_fence <= '0;
+ mem_is_fence_i <= '0;
+ end else if (~stall_en) begin
+ mem_alu_result <= ex_alu_result;
+ mem_branch_taken <= ex_branch_taken;
+ mem_branch_target <= ex_branch_target;
+ mem_rs1_rdata <= ex_rs1_rdata;
+ mem_rs2_rdata <= ex_rs2_rdata;
+ mem_rs1_addr <= ex_rs1_addr;
+ mem_pc <= ex_pc;
+ mem_imm <= ex_imm;
+
+ mem_is_load <= ex_is_load;
+ mem_is_store <= ex_is_store;
+ mem_mem_size <= ex_mem_size;
+ mem_reg_write_en <= ex_reg_write_en;
+ mem_rd_addr <= ex_rd_addr;
+ mem_wb_sel <= ex_wb_sel;
+
+ mem_is_csr <= ex_is_csr;
+ mem_csr_op <= ex_csr_op;
+ mem_illegal_instr <= ex_illegal_instr;
+ mem_is_ecall <= ex_is_ecall;
+ mem_is_ebreak <= ex_is_ebreak;
+ mem_is_mret <= ex_is_mret;
+ mem_is_sret <= ex_is_sret;
+ mem_is_wfi <= ex_is_wfi;
+ mem_is_sfence_vma <= ex_is_sfence_vma;
+ mem_is_fence <= ex_is_fence;
+ mem_is_fence_i <= ex_is_fence_i;
+ end
+ // If stall_en && !flush_en, maintain current state
+ end
+
+endmodule
diff --git a/rv64cpu/rtl/core/ex_stage.sv b/rv64cpu/rtl/core/ex_stage.sv
index 0991b50..48d4833 100644
--- a/rv64cpu/rtl/core/ex_stage.sv
+++ b/rv64cpu/rtl/core/ex_stage.sv
@@ -42,17 +42,17 @@ module ex_stage
output logic [XLEN-1:0] ex_branch_target
);
- logic [XLEN-1:0] alumux_a;
- logic [XLEN-1:0] alumux_b;
+ logic [XLEN-1:0] alu_mux_a;
+ logic [XLEN-1:0] alu_mux_b;
logic [XLEN-1:0] alu_operand_a;
logic [XLEN-1:0] alu_operand_b;
logic [XLEN-1:0] alu_raw_result;
- logic bu_branch_taken;
+ logic branch_unit_taken;
// -------------
// ALU Input Multiplexers (MUX)
- assign alumux_a = (ex_alu_src1_sel == 1'b1) ? ex_pc : ex_rs1_rdata;
- assign alumux_b = (ex_alu_src2_sel == 1'b1) ? ex_imm : ex_rs2_rdata;
+ assign alu_mux_a = (ex_alu_src1_sel == 1'b1) ? ex_pc : ex_rs1_rdata;
+ assign alu_mux_b = (ex_alu_src2_sel == 1'b1) ? ex_imm : ex_rs2_rdata;
// -------------
// RV64 Word Operation (32-bit) Pre-conditioning
@@ -62,21 +62,21 @@ module ex_stage
if (ex_is_word_op) begin
// Shift operations require specific 32-bit extension forms
if (ex_alu_op == ALU_SRA)
- alu_operand_a = { {32{alumux_a[31]}}, alumux_a[31:0] }; // Sign extend for arithmetic shift
+ alu_operand_a = { {32{alu_mux_a[31]}}, alu_mux_a[31:0] }; // Sign extend for arithmetic shift
else if (ex_alu_op == ALU_SRL)
- alu_operand_a = { 32'b0, alumux_a[31:0] }; // Zero extend for logical shift
+ alu_operand_a = { 32'b0, alu_mux_a[31:0] }; // Zero extend for logical shift
else
- alu_operand_a = alumux_a; // ADDW/SUBW/SLLW don't care about upper bits
+ alu_operand_a = alu_mux_a; // ADDW/SUBW/SLLW don't care about upper bits
// RV32 shift amount is strictly 5 bits (0-31), ignoring bit 5 which might be set in 64-bit registers
if (ex_alu_op == ALU_SLL || ex_alu_op == ALU_SRL || ex_alu_op == ALU_SRA)
- alu_operand_b = { 59'b0, alumux_b[4:0] };
+ alu_operand_b = { 59'b0, alu_mux_b[4:0] };
else
- alu_operand_b = alumux_b;
+ alu_operand_b = alu_mux_b;
end else begin
// 64-bit operations pass through unchanged
- alu_operand_a = alumux_a;
- alu_operand_b = alumux_b;
+ alu_operand_a = alu_mux_a;
+ alu_operand_b = alu_mux_b;
end
end
@@ -96,7 +96,7 @@ module ex_stage
.branch_op (ex_branch_op),
.operand_a (ex_rs1_rdata),
.operand_b (ex_rs2_rdata),
- .branch_taken (bu_branch_taken)
+ .branch_taken (branch_unit_taken)
);
// -------------
@@ -109,6 +109,6 @@ module ex_stage
// Branch Target Calculation
assign ex_branch_target = alu_raw_result & ~64'b1;
- assign ex_branch_taken = ex_is_jump | (ex_is_branch & bu_branch_taken);
+ assign ex_branch_taken = ex_is_jump | (ex_is_branch & branch_unit_taken);
endmodule
diff --git a/rv64cpu/rtl/core/id_ex_reg.sv b/rv64cpu/rtl/core/id_ex_reg.sv
index b8a3bd7..e88ce17 100644
--- a/rv64cpu/rtl/core/id_ex_reg.sv
+++ b/rv64cpu/rtl/core/id_ex_reg.sv
@@ -36,6 +36,8 @@ module id_ex_reg
input logic [XLEN-1:0] id_pc,
input logic [XLEN-1:0] id_rs1_rdata,
input logic [XLEN-1:0] id_rs2_rdata,
+ input logic [4:0] id_rs1_addr,
+ input logic [4:0] id_rs2_addr,
input logic [XLEN-1:0] id_imm,
// Execution Control
@@ -75,6 +77,8 @@ module id_ex_reg
output logic [XLEN-1:0] ex_pc,
output logic [XLEN-1:0] ex_rs1_rdata,
output logic [XLEN-1:0] ex_rs2_rdata,
+ output logic [4:0] ex_rs1_addr,
+ output logic [4:0] ex_rs2_addr,
output logic [XLEN-1:0] ex_imm,
// Execution Control
@@ -109,10 +113,12 @@ module id_ex_reg
);
always_ff @(posedge clk) begin
- if (rst || flush_en) begin
+ if (rst) begin
ex_pc <= '0;
ex_rs1_rdata <= '0;
ex_rs2_rdata <= '0;
+ ex_rs1_addr <= '0;
+ ex_rs2_addr <= '0;
ex_imm <= '0;
ex_alu_op <= ALU_ADD; // NOP is effectively ADD x0, x0, 0
ex_alu_src1_sel <= '0;
@@ -138,10 +144,37 @@ module id_ex_reg
ex_is_sfence_vma <= '0;
ex_is_fence <= '0;
ex_is_fence_i <= '0;
+ end else if (flush_en) begin
+ ex_alu_op <= ALU_ADD; // NOP is effectively ADD x0, x0, 0
+ ex_alu_src1_sel <= '0;
+ ex_alu_src2_sel <= '0;
+ ex_is_word_op <= '0;
+ ex_is_branch <= '0;
+ ex_branch_op <= BRANCH_EQ;
+ ex_is_jump <= '0;
+ ex_is_load <= '0;
+ ex_is_store <= '0;
+ ex_mem_size <= '0;
+ ex_reg_write_en <= '0; // VERY IMPORTANT: Do not write to regfile on NOP
+ ex_rd_addr <= '0;
+ ex_wb_sel <= '0;
+ ex_is_csr <= '0;
+ ex_csr_op <= '0;
+ ex_illegal_instr <= '0;
+ ex_is_ecall <= '0;
+ ex_is_ebreak <= '0;
+ ex_is_mret <= '0;
+ ex_is_sret <= '0;
+ ex_is_wfi <= '0;
+ ex_is_sfence_vma <= '0;
+ ex_is_fence <= '0;
+ ex_is_fence_i <= '0;
end else if (~stall_en) begin
ex_pc <= id_pc;
ex_rs1_rdata <= id_rs1_rdata;
ex_rs2_rdata <= id_rs2_rdata;
+ ex_rs1_addr <= id_rs1_addr;
+ ex_rs2_addr <= id_rs2_addr;
ex_imm <= id_imm;
ex_alu_op <= id_alu_op;
ex_alu_src1_sel <= id_alu_src1_sel;
diff --git a/rv64cpu/rtl/core/id_stage.sv b/rv64cpu/rtl/core/id_stage.sv
index 5e22662..27d3daf 100644
--- a/rv64cpu/rtl/core/id_stage.sv
+++ b/rv64cpu/rtl/core/id_stage.sv
@@ -38,6 +38,8 @@ module id_stage
output logic [XLEN-1:0] id_pc, // Pass-through PC for branch/jump calculation
output logic [XLEN-1:0] id_rs1_rdata, // Source register 1 data
output logic [XLEN-1:0] id_rs2_rdata, // Source register 2 data
+ output logic [4:0] id_rs1_addr, // Rs1 index (for Forwarding & CSR zimm)
+ output logic [4:0] id_rs2_addr, // Rs2 index (for Forwarding)
output logic [XLEN-1:0] id_imm, // Sign-extended generic immediate
// Execution Control (ALU & Branch)
@@ -74,8 +76,10 @@ module id_stage
logic [4:0] rs1_addr;
logic [4:0] rs2_addr;
- // Pass-through PC directly to next stage
+ // Pass-through PC and reg indices directly to next stage
assign id_pc = if_pc;
+ assign id_rs1_addr = rs1_addr;
+ assign id_rs2_addr = rs2_addr;
// Instruction Decoder Instantiation
diff --git a/rv64cpu/rtl/core/mem_stage.sv b/rv64cpu/rtl/core/mem_stage.sv
new file mode 100644
index 0000000..a63a456
--- /dev/null
+++ b/rv64cpu/rtl/core/mem_stage.sv
@@ -0,0 +1,214 @@
+// Richard CPU
+// Copyright (C) 2026 Richard Qin
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+// File path: rtl/core/mem_stage.sv
+// Description: Memory Stage
+// Latches results from the EX stage and bypassed control signals from ID/EX.
+// Supports stall and flush operations.
+
+module mem_stage
+ import rv64_pkg::*;
+(
+ // Inputs from EX/MEM pipeline register
+ input logic [XLEN-1:0] mem_alu_result, // Used as memory address or ALU result
+ input logic mem_branch_taken,
+ input logic [XLEN-1:0] mem_branch_target,
+ input logic [XLEN-1:0] mem_rs1_rdata,
+ input logic [XLEN-1:0] mem_rs2_rdata, // Store data
+ input logic [4:0] mem_rs1_addr,
+ input logic [XLEN-1:0] mem_pc,
+ input logic [XLEN-1:0] mem_imm,
+
+ // Memory Control
+ input logic mem_is_load,
+ input logic mem_is_store,
+ input logic [2:0] mem_mem_size, // LB/LH/LW/LD/LBU/LHU/LWU
+
+ // Writeback Control
+ input logic mem_reg_write_en,
+ input logic [4:0] mem_rd_addr,
+ input logic [1:0] mem_wb_sel,
+
+ // Exceptions and System (bypassed through or generated)
+ input logic mem_is_csr,
+ input logic [2:0] mem_csr_op,
+ input logic mem_illegal_instr,
+ input logic mem_is_ecall,
+ input logic mem_is_ebreak,
+ input logic mem_is_mret,
+ input logic mem_is_sret,
+ input logic mem_is_wfi,
+ input logic mem_is_sfence_vma,
+ input logic mem_is_fence,
+ input logic mem_is_fence_i,
+
+ // Data Memory Interface (to Data Cache / Memory Controller)
+ output logic dmem_read_req,
+ output logic dmem_write_req,
+ output logic [XLEN-1:0] dmem_addr,
+ output logic [XLEN-1:0] dmem_wdata,
+ output logic [7:0] dmem_wstrb, // Write strobe depending on size
+ input logic dmem_req_ready, // Wait signal from D-Cache
+ input logic dmem_rsp_valid, // Data valid from D-Cache
+ input logic [XLEN-1:0] dmem_rdata,
+
+ // Outputs to MEM/WB Pipeline Register
+ output logic [XLEN-1:0] mem_wb_alu_result,
+ output logic [XLEN-1:0] mem_wb_mem_rdata,
+ output logic [XLEN-1:0] mem_wb_pc,
+
+ output logic mem_wb_reg_write_en,
+ output logic [4:0] mem_wb_rd_addr,
+ output logic [1:0] mem_wb_wb_sel,
+
+ output logic mem_wb_is_csr,
+ output logic [2:0] mem_wb_csr_op,
+ output logic [XLEN-1:0] mem_wb_rs1_rdata,
+ output logic [4:0] mem_wb_rs1_addr,
+ output logic [XLEN-1:0] mem_wb_imm,
+
+ output logic mem_wb_illegal_instr,
+ output logic mem_wb_is_ecall,
+ output logic mem_wb_is_ebreak,
+ output logic mem_wb_is_mret,
+ output logic mem_wb_is_sret,
+
+ // Control to Hazard Unit / Stall Logic
+ output logic mem_stall_req // Stall pipeline if D-Cache doesn't respond
+);
+
+ logic [XLEN-1:0] load_data_aligned;
+ logic [XLEN-1:0] store_data_aligned;
+ logic [7:0] write_strobe;
+
+ // --------------------------
+ // Memory Request Logic
+ assign dmem_read_req = mem_is_load;
+ assign dmem_write_req = mem_is_store;
+ assign dmem_addr = mem_alu_result; // ALU result is the computed address
+
+ // --------------------------
+ // Stall generation: Stall if memory request is not yet ready or valid
+ // For a simple synchronous SRAM, this might be 0, but for cache it will depend on hits/misses
+ // --------------------------
+ always_comb begin
+ if ((mem_is_load || mem_is_store) && (!dmem_req_ready || (mem_is_load && !dmem_rsp_valid))) begin
+ mem_stall_req = 1'b1;
+ end else begin
+ mem_stall_req = 1'b0;
+ end
+ end
+
+ // --------------------------
+ // Store Data Alignment and Strobe Generation
+ // --------------------------
+ always_comb begin
+ logic [2:0] align_offset;
+ store_data_aligned = '0;
+ write_strobe = 8'b0000_0000;
+
+ // Mem address lower 3 bits determine the alignment within the 64-bit word
+ align_offset = mem_alu_result[2:0];
+
+ if (mem_is_store) begin
+ case (mem_mem_size)
+ // SB: Store Byte
+ 3'b000: begin
+ store_data_aligned = {56'b0, mem_rs2_rdata[7:0]} << (align_offset * 8);
+ write_strobe = 8'b0000_0001 << align_offset;
+ end
+ // SH: Store Halfword
+ 3'b001: begin
+ store_data_aligned = {48'b0, mem_rs2_rdata[15:0]} << (align_offset * 8);
+ write_strobe = 8'b0000_0011 << align_offset;
+ end
+ // SW: Store Word
+ 3'b010: begin
+ store_data_aligned = {32'b0, mem_rs2_rdata[31:0]} << (align_offset * 8);
+ write_strobe = 8'b0000_1111 << align_offset;
+ end
+ // SD: Store Doubleword
+ 3'b011: begin
+ store_data_aligned = mem_rs2_rdata;
+ write_strobe = 8'b1111_1111;
+ end
+ default: begin
+ store_data_aligned = '0;
+ write_strobe = 8'b0000_0000;
+ end
+ endcase
+ end
+ end
+
+ assign dmem_wdata = store_data_aligned;
+ assign dmem_wstrb = write_strobe;
+
+ // --------------------------
+ // Load Data Alignment and Sign/Zero Extension
+ // --------------------------
+ always_comb begin
+ logic [2:0] align_offset;
+ logic [XLEN-1:0] shifted_rdata;
+ load_data_aligned = '0;
+
+ align_offset = mem_alu_result[2:0];
+
+ // Shift data down so the target bytes are at the bottom
+ shifted_rdata = dmem_rdata >> (align_offset * 8);
+
+ case (mem_mem_size)
+ // LB: Load Byte (Sign extend)
+ 3'b000: load_data_aligned = { {56{shifted_rdata[7]}}, shifted_rdata[7:0] };
+ // LH: Load Halfword (Sign extend)
+ 3'b001: load_data_aligned = { {48{shifted_rdata[15]}}, shifted_rdata[15:0] };
+ // LW: Load Word (Sign extend)
+ 3'b010: load_data_aligned = { {32{shifted_rdata[31]}}, shifted_rdata[31:0] };
+ // LD: Load Doubleword
+ 3'b011: load_data_aligned = shifted_rdata;
+ // LBU: Load Byte Unsigned (Zero extend)
+ 3'b100: load_data_aligned = { 56'b0, shifted_rdata[7:0] };
+ // LHU: Load Half Unsigned (Zero extend)
+ 3'b101: load_data_aligned = { 48'b0, shifted_rdata[15:0] };
+ // LWU: Load Word Unsigned (Zero extend)
+ 3'b110: load_data_aligned = { 32'b0, shifted_rdata[31:0] };
+ default: load_data_aligned = '0;
+ endcase
+ end
+
+ // --------------------------
+ // Pass Output Signals to WB Stage
+ // --------------------------
+ assign mem_wb_alu_result = mem_alu_result;
+ assign mem_wb_mem_rdata = load_data_aligned;
+ assign mem_wb_pc = mem_pc;
+
+ assign mem_wb_reg_write_en = mem_reg_write_en;
+ assign mem_wb_rd_addr = mem_rd_addr;
+ assign mem_wb_wb_sel = mem_wb_sel;
+
+ assign mem_wb_is_csr = mem_is_csr;
+ assign mem_wb_csr_op = mem_csr_op;
+ assign mem_wb_rs1_rdata = mem_rs1_rdata;
+ assign mem_wb_rs1_addr = mem_rs1_addr;
+ assign mem_wb_imm = mem_imm;
+
+ assign mem_wb_illegal_instr = mem_illegal_instr;
+ assign mem_wb_is_ecall = mem_is_ecall;
+ assign mem_wb_is_ebreak = mem_is_ebreak;
+ assign mem_wb_is_mret = mem_is_mret;
+ assign mem_wb_is_sret = mem_is_sret;
+
+endmodule
diff --git a/rv64cpu/rtl/core/mem_wb_reg.sv b/rv64cpu/rtl/core/mem_wb_reg.sv
new file mode 100644
index 0000000..a70057c
--- /dev/null
+++ b/rv64cpu/rtl/core/mem_wb_reg.sv
@@ -0,0 +1,132 @@
+// Richard CPU
+// Copyright (C) 2026 Richard Qin
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+// File path: rtl/core/mem_wb_reg.sv
+// Description: MEM/WB pipeline stage register (Memory Access to Write Back)
+// Passes the final computation results, memory read data, and write-back control signals to the write-back stage
+
+module mem_wb_reg
+ import rv64_pkg::*;
+(
+ input logic clk,
+ input logic rst,
+
+ // -----------------------
+ // Control Signals from Hazard Unit
+ input logic stall_en,
+ input logic flush_en,
+
+ // -----------------------
+ // Inputs from MEM stage
+ // -----------------------
+ // Data and addresses
+ input logic [XLEN-1:0] mem_pc,
+ input logic [XLEN-1:0] mem_alu_result,
+ input logic [XLEN-1:0] mem_mem_rdata,
+
+ // Write back control
+ input logic mem_reg_write_en,
+ input logic [4:0] mem_rd_addr,
+ input logic [1:0] mem_wb_sel,
+
+ // CSR & System
+ input logic mem_is_csr,
+ input logic [2:0] mem_csr_op,
+ input logic [XLEN-1:0] mem_rs1_rdata,
+ input logic [4:0] mem_rs1_addr,
+ input logic [XLEN-1:0] mem_imm,
+ input logic mem_illegal_instr,
+ input logic mem_is_ecall,
+ input logic mem_is_ebreak,
+ input logic mem_is_mret,
+ input logic mem_is_sret,
+
+ // -----------------------
+ // Outputs to WB Stage
+ // -----------------------
+ // Data and address
+ output logic [XLEN-1:0] wb_pc,
+ output logic [XLEN-1:0] wb_alu_result,
+ output logic [XLEN-1:0] wb_mem_rdata,
+
+ // Write back control
+ output logic wb_reg_write_en,
+ output logic [4:0] wb_rd_addr,
+ output logic [1:0] wb_wb_sel,
+
+ // CSR & System
+ output logic wb_is_csr,
+ output logic [2:0] wb_csr_op,
+ output logic [XLEN-1:0] wb_rs1_rdata,
+ output logic [4:0] wb_rs1_addr,
+ output logic [XLEN-1:0] wb_imm,
+ output logic wb_illegal_instr,
+ output logic wb_is_ecall,
+ output logic wb_is_ebreak,
+ output logic wb_is_mret,
+ output logic wb_is_sret
+
+);
+ // Sequential Logic: State Update
+ always_ff @(posedge clk) begin
+ if (rst) begin
+ wb_pc <= '0;
+ wb_alu_result <= '0;
+ wb_mem_rdata <= '0;
+ wb_reg_write_en <= '0;
+ wb_rd_addr <= '0;
+ wb_wb_sel <= '0;
+ wb_is_csr <= '0;
+ wb_csr_op <= '0;
+ wb_rs1_rdata <= '0;
+ wb_rs1_addr <= '0;
+ wb_imm <= '0;
+ wb_illegal_instr <= '0;
+ wb_is_ecall <= '0;
+ wb_is_ebreak <= '0;
+ wb_is_mret <= '0;
+ wb_is_sret <= '0;
+ end else if (flush_en) begin
+ // Target specific control signals to clear. Leave datapath elements intact
+ // to avoid extreme power consumption from massive flip-flop state changes array.
+ wb_reg_write_en <= '0;
+ wb_is_csr <= '0;
+ wb_illegal_instr <= '0;
+ wb_is_ecall <= '0;
+ wb_is_ebreak <= '0;
+ wb_is_mret <= '0;
+ wb_is_sret <= '0;
+ end else if (!stall_en) begin
+ wb_pc <= mem_pc;
+ wb_alu_result <= mem_alu_result;
+ wb_mem_rdata <= mem_mem_rdata;
+ wb_reg_write_en <= mem_reg_write_en;
+ wb_rd_addr <= mem_rd_addr;
+ wb_wb_sel <= mem_wb_sel;
+ wb_is_csr <= mem_is_csr;
+ wb_csr_op <= mem_csr_op;
+ wb_rs1_rdata <= mem_rs1_rdata;
+ wb_rs1_addr <= mem_rs1_addr;
+ wb_imm <= mem_imm;
+ wb_illegal_instr <= mem_illegal_instr;
+ wb_is_ecall <= mem_is_ecall;
+ wb_is_ebreak <= mem_is_ebreak;
+ wb_is_mret <= mem_is_mret;
+ wb_is_sret <= mem_is_sret;
+ end
+ end
+
+endmodule
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